From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 23 Nov 2019 16:38:48 +0000 (-0800)
Subject: Merge branch 'xaig_dff' of github.com:YosysHQ/yosys into xaig_dff
X-Git-Tag: working-ls180~881^2^2~145
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b46e636c9142ef69ed1b76e9f968716a258aff46;p=yosys.git

Merge branch 'xaig_dff' of github.com:YosysHQ/yosys into xaig_dff
---

b46e636c9142ef69ed1b76e9f968716a258aff46
diff --cc tests/simple_abc9/abc9.v
index 8314af211,65eb01338..99075d319
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@@ -268,7 -268,12 +268,12 @@@ assign o = { 1'b1, 1'bx }
  assign p = { 1'b1, 1'bx, 1'b0 };
  endmodule
  
- module abc9_test029(input clk, d, r, output reg q);
 -module abc9_test029(input clk1, clk2, input d, output reg q1, q2);
++module abc9_test029(input clk1, clk2, d, output reg q1, q2);
+ always @(posedge clk1) q1 <= d;
+ always @(negedge clk2) q2 <= q1;
+ endmodule
+ 
+ module abc9_test030(input clk, d, r, output reg q);
  always @(posedge clk or posedge r)
      if (r) q <= 1'b0;
      else q <= d;
@@@ -279,18 -284,3 +284,13 @@@ always @(negedge clk or posedge r
      if (r) q <= 1'b1;
      else q <= d;
  endmodule
 +
- module abc9_test032(input clk1, clk2, d, output reg q1, q2);
- always @(posedge clk1) q1 <= d;
- always @(negedge clk2) q2 <= q1;
- endmodule
- 
 +module abc9_test033(input clk, d, output reg q1, q2);
 +always @(posedge clk) q1 <= d;
 +always @(posedge clk) q2 <= q1;
 +endmodule
 +
 +module abc9_test034(input clk, d, output reg [1:0] q);
 +always @(posedge clk) q[0] <= d;
 +always @(negedge clk) q[1] <= q[0];
 +endmodule