From: Michael Neuling Date: Fri, 25 Feb 2022 00:08:57 +0000 (+1100) Subject: Merge pull request #349 from madscientist159/master X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b4770197a2e07c321f283d8882a3dcb380a1344b;p=microwatt.git Merge pull request #349 from madscientist159/master Extend LiteDRAM VHDL wrapper to allow more than one clock line --- b4770197a2e07c321f283d8882a3dcb380a1344b