From: Luke Kenneth Casson Leighton Date: Sun, 19 May 2019 15:11:51 +0000 (+0100) Subject: add reg clearing and read-request release X-Git-Tag: div_pipeline~2012 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b48173a5184d230f56e51d3b61677048d448db00;p=soc.git add reg clearing and read-request release --- diff --git a/src/experiment/compalu.py b/src/experiment/compalu.py index d03a8d2c..016b9104 100644 --- a/src/experiment/compalu.py +++ b/src/experiment/compalu.py @@ -21,6 +21,7 @@ class ComputationUnitNoDelay(Elaboratable): self.busy_o = Signal(reset_less=True) # fn busy out self.data_o = Signal(rwid, reset_less=True) # Dest out + self.rd_rel_o = Signal(reset_less=True) # release src1/src2 request self.req_rel_o = Signal(reset_less=True) # release request out (valid_o) def elaborate(self, platform): @@ -52,6 +53,7 @@ class ComputationUnitNoDelay(Elaboratable): # outputs m.d.comb += self.busy_o.eq(opc_l.q) # busy out + m.d.comb += self.rd_rel_o.eq(src_l.q & opc_l.q) # src1/src2 req rel with m.If(req_l.qn & opc_l.q & (self.counter == 0)): m.d.sync += self.counter.eq(3) diff --git a/src/experiment/cscore.py b/src/experiment/cscore.py index 7f692aac..cbc76f99 100644 --- a/src/experiment/cscore.py +++ b/src/experiment/cscore.py @@ -197,8 +197,8 @@ class Scoreboard(Elaboratable): #--------- readable_o = intfudeps.readable_o writable_o = intfudeps.writable_o - m.d.comb += intpick1.go_rd_i[0].eq(~if_l[0].go_rd_i) - m.d.comb += intpick1.go_rd_i[1].eq(~if_l[1].go_rd_i) + m.d.comb += intpick1.rd_rel_i[0].eq(fn_busy_l[0]) + m.d.comb += intpick1.rd_rel_i[1].eq(fn_busy_l[1]) m.d.comb += intpick1.req_rel_i[0].eq(int_alus[0].req_rel_o) m.d.comb += intpick1.req_rel_i[1].eq(int_alus[1].req_rel_o) m.d.comb += intpick1.readable_i[0].eq(readable_o[0]) # add rd diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py index 078c2b5b..b5f37bb9 100644 --- a/src/experiment/score6600.py +++ b/src/experiment/score6600.py @@ -32,6 +32,7 @@ class CompUnits(Elaboratable): self.go_rd_i = Signal(n_units, reset_less=True) self.go_wr_i = Signal(n_units, reset_less=True) self.busy_o = Signal(n_units, reset_less=True) + self.rd_rel_o = Signal(n_units, reset_less=True) self.req_rel_o = Signal(n_units, reset_less=True) self.dest_o = Signal(rwid, reset_less=True) @@ -56,12 +57,15 @@ class CompUnits(Elaboratable): issue_l = [] busy_l = [] req_rel_l = [] + rd_rel_l = [] for alu in int_alus: req_rel_l.append(alu.req_rel_o) + rd_rel_l.append(alu.rd_rel_o) go_wr_l.append(alu.go_wr_i) go_rd_l.append(alu.go_rd_i) issue_l.append(alu.issue_i) busy_l.append(alu.busy_o) + m.d.comb += self.rd_rel_o.eq(Cat(*rd_rel_l)) m.d.comb += self.req_rel_o.eq(Cat(*req_rel_l)) m.d.comb += self.busy_o.eq(Cat(*busy_l)) m.d.comb += Cat(*go_wr_l).eq(self.go_wr_i) @@ -166,6 +170,7 @@ class Scoreboard(Elaboratable): self.int_dest_i = Signal(max=n_regs, reset_less=True) # Dest R# in self.int_src1_i = Signal(max=n_regs, reset_less=True) # oper1 R# in self.int_src2_i = Signal(max=n_regs, reset_less=True) # oper2 R# in + self.reg_enable_i = Signal(reset_less=True) # enable reg decode self.issue_o = Signal(reset_less=True) # instruction was accepted @@ -218,7 +223,7 @@ class Scoreboard(Elaboratable): regdecode.dest_i.eq(self.int_dest_i), regdecode.src1_i.eq(self.int_src1_i), regdecode.src2_i.eq(self.int_src2_i), - regdecode.enable_i.eq(1), + regdecode.enable_i.eq(self.reg_enable_i), issueunit.i.dest_i.eq(regdecode.dest_o), self.issue_o.eq(issueunit.issue_o) ] @@ -253,7 +258,8 @@ class Scoreboard(Elaboratable): # Connect Picker #--------- - m.d.comb += intpick1.rd_rel_i[0:2].eq(~go_rd_i[0:2] & cu.busy_o[0:2]) + #m.d.comb += intpick1.rd_rel_i[0:2].eq(~go_rd_i[0:2] & cu.busy_o[0:2]) + m.d.comb += intpick1.rd_rel_i[0:2].eq(cu.rd_rel_o[0:2]) #m.d.comb += intpick1.go_rd_i[0:2].eq(cu.req_rel_o[0:2]) m.d.comb += intpick1.req_rel_i[0:2].eq(cu.req_rel_o[0:2]) int_readable_o = intfus.readable_o @@ -342,6 +348,7 @@ def int_instr(dut, alusim, op, src1, src2, dest): yield dut.int_src1_i.eq(src1) yield dut.int_src2_i.eq(src2) yield dut.int_insn_i[op].eq(1) + yield dut.reg_enable_i.eq(1) alusim.op(op, src1, src2, dest) @@ -361,8 +368,6 @@ def scoreboard_sim(dut, alusim): yield dut.intregs.regs[i].reg.eq(4+i*2) alusim.setval(i, 4+i*2) - yield - instrs = [] if False: for i in range(2): @@ -403,10 +408,10 @@ def scoreboard_sim(dut, alusim): yield from print_reg(dut, [3,4,5]) for i in range(len(dut.int_insn_i)): yield dut.int_insn_i[i].eq(0) + yield dut.reg_enable_i.eq(0) break print ("busy",) yield from print_reg(dut, [3,4,5]) - yield yield yield from print_reg(dut, [3,4,5]) diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py index d0dbbefc..cc49ab4e 100644 --- a/src/scoreboard/dependence_cell.py +++ b/src/scoreboard/dependence_cell.py @@ -33,7 +33,7 @@ class DepCell(Elaboratable): m.d.comb += l.r.eq(self.go_i) # Function Unit "Forward Progress". - m.d.comb += self.fwd_o.eq((cq | l.q) & self.reg_i) + m.d.comb += self.fwd_o.eq((l.q) & self.reg_i & ~self.issue_i) # Register Select. Activated on go read/write and *current* latch set m.d.comb += self.rsel_o.eq((cq | l.q) & self.go_i) @@ -83,7 +83,7 @@ class DependenceCell(Elaboratable): # connect issue for c in [dest_c, src1_c, src2_c]: m.d.comb += c.issue_i.eq(self.issue_i) - + # connect go_rd / go_wr (dest->wr, src->rd) m.d.comb += dest_c.go_i.eq(self.go_wr_i) m.d.comb += src1_c.go_i.eq(self.go_rd_i) diff --git a/src/scoreboard/fu_picker_vec.py b/src/scoreboard/fu_picker_vec.py index fd44c45f..7fe5d5a0 100644 --- a/src/scoreboard/fu_picker_vec.py +++ b/src/scoreboard/fu_picker_vec.py @@ -15,7 +15,7 @@ class FU_Pick_Vec(Elaboratable): def elaborate(self, platform): m = Module() - m.d.comb += self.readable_o.eq(self.rd_pend_i.bool()) - m.d.comb += self.writable_o.eq(self.wr_pend_i.bool()) + m.d.comb += self.readable_o.eq(~self.rd_pend_i.bool()) + m.d.comb += self.writable_o.eq(~self.wr_pend_i.bool()) return m diff --git a/src/scoreboard/issue_unit.py b/src/scoreboard/issue_unit.py index ade35d76..4f010b4b 100644 --- a/src/scoreboard/issue_unit.py +++ b/src/scoreboard/issue_unit.py @@ -111,6 +111,7 @@ class IssueUnit(Elaboratable): yield self.dest_i yield self.src1_i yield self.src2_i + yield self.reg_enable_i yield self.g_wr_pend_i yield from self.insn_i yield from self.busy_i @@ -128,10 +129,10 @@ class IntFPIssueUnit(Elaboratable): self.issue_o = Signal(reset_less=True) # some renames - self.int_write_pending_i = self.i.g_wr_pend_i - self.fp_write_pending_i = self.f.g_wr_pend_i - self.int_write_pending_i.name = 'int_write_pending_i' - self.fp_write_pending_i.name = 'fp_write_pending_i' + self.int_wr_pend_i = self.i.g_wr_pend_i + self.fp_wr_pend_i = self.f.g_wr_pend_i + self.int_wr_pend_i.name = 'int_wr_pend_i' + self.fp_wr_pend_i.name = 'fp_wr_pend_i' def elaborate(self, platform): m = Module()