From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 27 Apr 2019 13:57:50 +0000 (+0100)
Subject: add submodules
X-Git-Tag: ls180-24jan2020~1181
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b48ce87fd6186963e5d5b8d63b50f6ba8798228d;p=ieee754fpu.git

add submodules
---

diff --git a/src/add/test_fsm_experiment.py b/src/add/test_fsm_experiment.py
index 782fc612..4d05bba8 100644
--- a/src/add/test_fsm_experiment.py
+++ b/src/add/test_fsm_experiment.py
@@ -19,7 +19,6 @@ class FPDIV(FPBase):
         self.width = width
 
         self.in_a  = FPOpIn(width)
-        self.in_b  = FPOpIn(width)
         self.out_z = FPOpOut(width)
 
         self.states = []
@@ -37,7 +36,9 @@ class FPDIV(FPBase):
         a = FPNumIn(None, self.width, False)
         z = FPNumOut(self.width, False)
 
-        m.submodules.in_a = a
+        m.submodules.in_a = self.in_a
+        m.submodules.out_z = self.out_z
+        m.submodules.a = a
         m.submodules.z = z
 
         m.d.comb += a.v.eq(self.in_a.v)