From: Tom Stellard <thomas.stellard@amd.com>
Date: Wed, 1 Aug 2012 16:20:20 +0000 (+0000)
Subject: radeon/llvm: Inline immediate offset when lowering implicit parameters
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b49771970bb8d06a179da69a7eb6b0af1b379d2d;p=mesa.git

radeon/llvm: Inline immediate offset when lowering implicit parameters
---

diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp b/src/gallium/drivers/radeon/R600ISelLowering.cpp
index 4d8c928f49b..7f79359fb21 100644
--- a/src/gallium/drivers/radeon/R600ISelLowering.cpp
+++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp
@@ -254,18 +254,22 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
 void R600TargetLowering::lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB,
     MachineRegisterInfo & MRI, unsigned dword_offset) const
 {
+  unsigned ByteOffset = dword_offset * 4;
+
+  // We shouldn't be using an offset wider than 16-bits for implicit parameters.
+  assert(isInt<16>(ByteOffset));
+
   MachineBasicBlock::iterator I = *MI;
   unsigned PtrReg = MRI.createVirtualRegister(&AMDGPU::R600_TReg32_XRegClass);
   MRI.setRegClass(MI->getOperand(0).getReg(), &AMDGPU::R600_TReg32_XRegClass);
 
-  BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::MOV), PtrReg)
-          .addReg(AMDGPU::ALU_LITERAL_X)
-          .addImm(dword_offset * 4);
+  BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::COPY), PtrReg)
+          .addReg(AMDGPU::ZERO);
 
   BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::VTX_READ_PARAM_i32_eg))
           .addOperand(MI->getOperand(0))
           .addReg(PtrReg)
-          .addImm(0);
+          .addImm(ByteOffset);
 }
 
 //===----------------------------------------------------------------------===//