From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Sat, 17 Sep 2022 20:48:34 +0000 (+0300)
Subject: power_insn: fix sat checks
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b49aa01b4c7d5b76995458b40cbd345d520cbb73;p=openpower-isa.git

power_insn: fix sat checks
---

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index 2062d07a..a86e281f 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -1356,7 +1356,7 @@ class NormalSaturationRM(NormalBaseRM):
             yield f"dz"
         if self.sz:
             yield f"sz"
-        if self.sat:
+        if self.N:
             yield "sats"
         else:
             yield "satu"
@@ -1374,7 +1374,7 @@ class NormalSaturationExtRM(NormalBaseRM):
     def specifiers(self):
         if self.zz:
             yield f"zz"
-        if self.sat:
+        if self.N:
             yield "sats"
         else:
             yield "satu"
@@ -1458,7 +1458,7 @@ class LDSTImmSaturationRM(LDSTImmBaseRM):
     def specifiers(self):
         if self.zz:
             yield f"zz"
-        if self.sat:
+        if self.N:
             yield "sats"
         else:
             yield "satu"
@@ -1533,7 +1533,7 @@ class LDSTIdxSaturationRM(LDSTIdxBaseRM):
             yield f"dz"
         if self.sz:
             yield f"sz"
-        if self.sat:
+        if self.N:
             yield "sats"
         else:
             yield "satu"