From: Marcelina Kościelnicka <mwk@0x04.net>
Date: Wed, 5 Aug 2020 10:28:18 +0000 (+0200)
Subject: techmap.CONSTMAP: Handle outputs before inputs.
X-Git-Tag: working-ls180~313^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b4a4cb081de717a7f6de89914f8f5ffec959b0c3;p=yosys.git

techmap.CONSTMAP: Handle outputs before inputs.

Fixes #2321.
---

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index c22ae8ef0..8d16a2bae 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -801,11 +801,31 @@ struct TechmapWorker
 									}
 								}
 
+								// Handle outputs first, as these cannot be remapped.
 								for (auto &conn : cell->connections())
+								{
+									Wire *twire = tpl->wire(conn.first);
+									if (!twire->port_output)
+										continue;
+
+									for (int i = 0; i < GetSize(conn.second); i++) {
+										RTLIL::SigBit bit = sigmap(conn.second[i]);
+										RTLIL::SigBit tplbit(twire, i);
+										cellbits_to_tplbits[bit] = tplbit;
+									}
+								}
+
+								// Now handle inputs, remapping as necessary.
+								for (auto &conn : cell->connections())
+								{
+									Wire *twire = tpl->wire(conn.first);
+									if (twire->port_output)
+										continue;
+
 									for (int i = 0; i < GetSize(conn.second); i++)
 									{
 										RTLIL::SigBit bit = sigmap(conn.second[i]);
-										RTLIL::SigBit tplbit(tpl->wire(conn.first), i);
+										RTLIL::SigBit tplbit(twire, i);
 
 										if (bit.wire == nullptr)
 										{
@@ -820,6 +840,7 @@ struct TechmapWorker
 										else
 											cellbits_to_tplbits[bit] = tplbit;
 									}
+								}
 
 								RTLIL::SigSig port_conn;
 								for (auto &it : port_connmap) {
diff --git a/tests/techmap/bug2321.ys b/tests/techmap/bug2321.ys
new file mode 100644
index 000000000..637528b21
--- /dev/null
+++ b/tests/techmap/bug2321.ys
@@ -0,0 +1,15 @@
+read_verilog <<EOT
+module m (input i, output o);
+wire [1023:0] _TECHMAP_DO_00_ = "CONSTMAP; ";
+endmodule
+EOT
+
+design -stash map
+
+read_verilog <<EOT
+module top(output o);
+m m (.o(o), .i(o));
+endmodule
+EOT
+
+techmap -map %map