From: Luke Kenneth Casson Leighton Date: Sun, 3 May 2020 14:59:20 +0000 (+0100) Subject: mention concurrent units, update regfile image to double-up the pipelines X-Git-Tag: convert-csv-opcode-to-binary~2764 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b4aa86c6dd17e22ba2ee6df7c3a6da5f74bda2a9;p=libreriscv.git mention concurrent units, update regfile image to double-up the pipelines --- diff --git a/3d_gpu/architecture/regfile.mdwn b/3d_gpu/architecture/regfile.mdwn index b59ebad67..444f62da0 100644 --- a/3d_gpu/architecture/regfile.mdwn +++ b/3d_gpu/architecture/regfile.mdwn @@ -24,8 +24,9 @@ This then requires some Bus Architecture to connect and keep the pipelines busy. Below is the connectivity diagram: * A single Dynamic PartitionedSignal capable 64-bit-wide pipeline is at the - top (a second Dynamic pipeline is off-page, with its own FUs) -* A **pair** of 32-bit Function Units connect to the (shared) pipeline. + top left and top right. +* Multiple **pairs** of 32-bit Function Units (making up a 64-bit data + path) connect, as "Concurrent Units", to each pipeline. * The number of **pairs** of Function Units **must** match (or preferably exceed) the number of pipeline stages. * Connected to each of the Operand and Result Ports on each Function Unit @@ -64,5 +65,6 @@ Notes: of an FMAC is extended by 3 cycles: this being the fact that only one CDB is available to deliver operands. +Click on the image to expand it full-screen: [[!img regfile_hilo_32_odd_even.png size="500px"]] diff --git a/3d_gpu/regfile_hilo_32_odd_even.png b/3d_gpu/regfile_hilo_32_odd_even.png index c2d7f2688..7fa3e426c 100644 Binary files a/3d_gpu/regfile_hilo_32_odd_even.png and b/3d_gpu/regfile_hilo_32_odd_even.png differ