From: Jacob Lifshay Date: Mon, 4 Dec 2023 09:43:26 +0000 (-0800) Subject: major/minor_62: add FIXMEs to lq/stq to match the FIXMEs on lqarx/stqcx. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b4ae658c25c294863788010eb885a63f4da68afa;p=openpower-isa.git major/minor_62: add FIXMEs to lq/stq to match the FIXMEs on lqarx/stqcx. --- diff --git a/openpower/isatables/major.csv b/openpower/isatables/major.csv index 6fd8c26a..2c341547 100644 --- a/openpower/isatables/major.csv +++ b/openpower/isatables/major.csv @@ -21,7 +21,7 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou 41,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,lhzu,D,,, 32,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,lwz,D,,, 33,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,0,0,NONE,0,1,lwzu,D,,, -56,LDST,OP_LOAD,RA_OR_ZERO,CONST_DQ,NONE,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,lq,DQ,,, +56,LDST,OP_LOAD,RA_OR_ZERO,CONST_DQ,NONE,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,lq,DQ,,,FIXME: should probably be is16B and RTp 7,MUL,OP_MUL_L64,RA,CONST_SI,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,NONE,0,0,mulli,D,,, 24,LOGICAL,OP_OR,RS,CONST_UI,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,ori,D,,, 25,LOGICAL,OP_OR,RS,CONST_UI_HI,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,oris,D,,, diff --git a/openpower/isatables/minor_62.csv b/openpower/isatables/minor_62.csv index 8fc19f5f..f2e3eec3 100644 --- a/openpower/isatables/minor_62.csv +++ b/openpower/isatables/minor_62.csv @@ -3,4 +3,4 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS,unofficial,comment2 0,LDST,OP_STORE,RA_OR_ZERO,CONST_DS,RS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,std,DS,,, 1,LDST,OP_STORE,RA_OR_ZERO,CONST_DS,RS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,stdu,DS,,, -2,LDST,OP_STORE,RA_OR_ZERO,CONST_DS,RS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,stq,DS,,, +2,LDST,OP_STORE,RA_OR_ZERO,CONST_DS,RS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,stq,DS,,,FIXME: should probably be is16B and RSp