From: Jeff Law <law@redhat.com>
Date: Thu, 16 Jan 1997 18:28:46 +0000 (+0000)
Subject:         * simops.c: Fix "rol" and "ror".
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b4b290a02065d796b8803193deb57422b2a035c4;p=binutils-gdb.git

    * simops.c: Fix "rol" and "ror".
Something I noticed while working on the mn10200.
---

diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog
index e871835a210..8a488e6deeb 100644
--- a/sim/mn10300/ChangeLog
+++ b/sim/mn10300/ChangeLog
@@ -1,3 +1,11 @@
+Thu Jan 16 11:28:14 1997  Jeffrey A Law  (law@cygnus.com)
+
+	* simops.c: Fix "rol" and "ror".
+
+Wed Jan 15 06:45:58 1997  Jeffrey A Law  (law@cygnus.com)
+
+	* simops.c: Fix typo in last change.
+
 Mon Jan 13 13:22:35 1997  Jeffrey A Law  (law@cygnus.com)
 
 	* simops.c: Use REG macros in few places not using them yet.
diff --git a/sim/mn10300/simops.c b/sim/mn10300/simops.c
index caa2d75136e..26146a159af 100644
--- a/sim/mn10300/simops.c
+++ b/sim/mn10300/simops.c
@@ -2219,7 +2219,7 @@ void OP_F284 (insn, extension)
   c = (value & 0x1);
 
   value >>= 1;
-  value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
+  value |= (c) ? 0x80000000 : 0;
   State.regs[REG_D0 + REG0 (insn)] = value;
   z = (value == 0);
   n = (value & 0x80000000) != 0;
@@ -2238,7 +2238,7 @@ void OP_F280 (insn, extension)
   c = (value & 0x80000000) ? 1 : 0;
 
   value <<= 1;
-  value |= ((PSW & PSW_C) != 0);
+  value |= c;
   State.regs[REG_D0 + REG0 (insn)] = value;
   z = (value == 0);
   n = (value & 0x80000000) != 0;