From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Mon, 29 Feb 2016 04:40:11 +0000 (-0800)
Subject: New definitions of misa/marchid/mvendorid
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b4bc2159c25688928c96c05ac3523ab1f8352a28;p=riscv-isa-sim.git

New definitions of misa/marchid/mvendorid
---

diff --git a/riscv/encoding.h b/riscv/encoding.h
index b2ef0bf..411a7af 100644
--- a/riscv/encoding.h
+++ b/riscv/encoding.h
@@ -64,8 +64,6 @@
 #define IRQ_COP      8
 #define IRQ_HOST     9
 
-#define IMPL_ROCKET 1
-
 #define DEFAULT_RSTVEC 0x0
 #define DEFAULT_NMIVEC 0x4
 #define DEFAULT_MTVEC  0x8
@@ -640,8 +638,8 @@
 #define CSR_UARCH14 0xcce
 #define CSR_UARCH15 0xccf
 #define CSR_SSTATUS 0x100
-#define CSR_STVEC 0x101
 #define CSR_SIE 0x104
+#define CSR_STVEC 0x105
 #define CSR_SSCRATCH 0x140
 #define CSR_SEPC 0x141
 #define CSR_SCAUSE 0x142
@@ -655,10 +653,10 @@
 #define CSR_STIME 0xd01
 #define CSR_STIMEW 0xa01
 #define CSR_MSTATUS 0x300
-#define CSR_MTVEC 0x301
 #define CSR_MEDELEG 0x302
 #define CSR_MIDELEG 0x303
 #define CSR_MIE 0x304
+#define CSR_MTVEC 0x305
 #define CSR_MTIMECMP 0x321
 #define CSR_MSCRATCH 0x340
 #define CSR_MEPC 0x341
@@ -667,13 +665,15 @@
 #define CSR_MIP 0x344
 #define CSR_MIPI 0x345
 #define CSR_MTIME 0x701
-#define CSR_MCPUID 0xf00
-#define CSR_MIMPID 0xf01
+#define CSR_MISA 0xf00
+#define CSR_MVENDORID 0xf01
+#define CSR_MARCHID 0xf02
+#define CSR_MIMPID 0xf03
+#define CSR_MCFGADDR 0xf04
 #define CSR_MHARTID 0xf10
 #define CSR_MTOHOST 0x7c0
 #define CSR_MFROMHOST 0x7c1
 #define CSR_MRESET 0x7c2
-#define CSR_MIOBASE 0x7c4
 #define CSR_CYCLEH 0xc80
 #define CSR_TIMEH 0xc81
 #define CSR_INSTRETH 0xc82
@@ -949,8 +949,8 @@ DECLARE_CSR(uarch13, CSR_UARCH13)
 DECLARE_CSR(uarch14, CSR_UARCH14)
 DECLARE_CSR(uarch15, CSR_UARCH15)
 DECLARE_CSR(sstatus, CSR_SSTATUS)
-DECLARE_CSR(stvec, CSR_STVEC)
 DECLARE_CSR(sie, CSR_SIE)
+DECLARE_CSR(stvec, CSR_STVEC)
 DECLARE_CSR(sscratch, CSR_SSCRATCH)
 DECLARE_CSR(sepc, CSR_SEPC)
 DECLARE_CSR(scause, CSR_SCAUSE)
@@ -964,10 +964,10 @@ DECLARE_CSR(instretw, CSR_INSTRETW)
 DECLARE_CSR(stime, CSR_STIME)
 DECLARE_CSR(stimew, CSR_STIMEW)
 DECLARE_CSR(mstatus, CSR_MSTATUS)
-DECLARE_CSR(mtvec, CSR_MTVEC)
 DECLARE_CSR(medeleg, CSR_MEDELEG)
 DECLARE_CSR(mideleg, CSR_MIDELEG)
 DECLARE_CSR(mie, CSR_MIE)
+DECLARE_CSR(mtvec, CSR_MTVEC)
 DECLARE_CSR(mtimecmp, CSR_MTIMECMP)
 DECLARE_CSR(mscratch, CSR_MSCRATCH)
 DECLARE_CSR(mepc, CSR_MEPC)
@@ -976,13 +976,15 @@ DECLARE_CSR(mbadaddr, CSR_MBADADDR)
 DECLARE_CSR(mip, CSR_MIP)
 DECLARE_CSR(mipi, CSR_MIPI)
 DECLARE_CSR(mtime, CSR_MTIME)
-DECLARE_CSR(mcpuid, CSR_MCPUID)
+DECLARE_CSR(misa, CSR_MISA)
+DECLARE_CSR(mvendorid, CSR_MVENDORID)
+DECLARE_CSR(marchid, CSR_MARCHID)
 DECLARE_CSR(mimpid, CSR_MIMPID)
+DECLARE_CSR(mcfgaddr, CSR_MCFGADDR)
 DECLARE_CSR(mhartid, CSR_MHARTID)
 DECLARE_CSR(mtohost, CSR_MTOHOST)
 DECLARE_CSR(mfromhost, CSR_MFROMHOST)
 DECLARE_CSR(mreset, CSR_MRESET)
-DECLARE_CSR(miobase, CSR_MIOBASE)
 DECLARE_CSR(cycleh, CSR_CYCLEH)
 DECLARE_CSR(timeh, CSR_TIMEH)
 DECLARE_CSR(instreth, CSR_INSTRETH)
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 0673787..f60d00a 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -64,10 +64,10 @@ void processor_t::parse_isa_string(const char* str)
   const char* all_subsets = "imafdc";
 
   max_xlen = 64;
-  cpuid = reg_t(2) << 62;
+  isa = reg_t(2) << 62;
 
   if (strncmp(p, "rv32", 4) == 0)
-    max_xlen = 32, cpuid = 0, p += 4;
+    max_xlen = 32, isa = 0, p += 4;
   else if (strncmp(p, "rv64", 4) == 0)
     p += 4;
   else if (strncmp(p, "rv", 2) == 0)
@@ -82,11 +82,11 @@ void processor_t::parse_isa_string(const char* str)
     bad_isa_string(str);
   }
 
-  isa = "rv" + std::to_string(max_xlen) + p;
-  cpuid |= 1L << ('s' - 'a'); // advertise support for supervisor mode
+  isa_string = "rv" + std::to_string(max_xlen) + p;
+  isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
 
   while (*p) {
-    cpuid |= 1L << (*p - 'a');
+    isa |= 1L << (*p - 'a');
 
     if (auto next = strchr(all_subsets, *p)) {
       all_subsets = next + 1;
@@ -104,6 +104,15 @@ void processor_t::parse_isa_string(const char* str)
 
   if (supports_extension('D') && !supports_extension('F'))
     bad_isa_string(str);
+
+  // if we have IMAFD, advertise G, too
+  if (supports_extension('I') && supports_extension('M') &&
+      supports_extension('A') && supports_extension('D'))
+    isa |= 1L << ('g' - 'a');
+
+  // advertise support for supervisor and user modes
+  isa |= 1L << ('s' - 'a');
+  isa |= 1L << ('u' - 'a');
 }
 
 void state_t::reset()
@@ -473,8 +482,10 @@ reg_t processor_t::get_csr(int which)
     case CSR_MCAUSE: return state.mcause;
     case CSR_MBADADDR: return state.mbadaddr;
     case CSR_MTIMECMP: return state.mtimecmp;
-    case CSR_MCPUID: return cpuid;
-    case CSR_MIMPID: return IMPL_ROCKET;
+    case CSR_MISA: return isa;
+    case CSR_MARCHID: return 0;
+    case CSR_MIMPID: return 0;
+    case CSR_MVENDORID: return 0;
     case CSR_MHARTID: return id;
     case CSR_MTVEC: return DEFAULT_MTVEC;
     case CSR_MEDELEG: return state.medeleg;
@@ -485,7 +496,7 @@ reg_t processor_t::get_csr(int which)
     case CSR_MFROMHOST:
       sim->get_htif()->tick(); // not necessary, but faster
       return state.fromhost;
-    case CSR_MIOBASE: return sim->memsz;
+    case CSR_MCFGADDR: return sim->memsz;
     case CSR_UARCH0:
     case CSR_UARCH1:
     case CSR_UARCH2:
diff --git a/riscv/processor.h b/riscv/processor.h
index 80cea36..b01d5bf 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -95,7 +95,7 @@ public:
   extension_t* get_extension() { return ext; }
   bool supports_extension(unsigned char ext) {
     if (ext >= 'a' && ext <= 'z') ext += 'A' - 'a';
-    return ext >= 'A' && ext <= 'Z' && ((cpuid >> (ext - 'A')) & 1);
+    return ext >= 'A' && ext <= 'Z' && ((isa >> (ext - 'A')) & 1);
   }
   void set_privilege(reg_t);
   void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
@@ -114,11 +114,11 @@ private:
   extension_t* ext;
   disassembler_t* disassembler;
   state_t state;
-  reg_t cpuid;
   uint32_t id;
   unsigned max_xlen;
   unsigned xlen;
-  std::string isa;
+  reg_t isa;
+  std::string isa_string;
   bool run; // !reset
   bool debug;
   bool histogram_enabled;
diff --git a/riscv/sim.cc b/riscv/sim.cc
index 69d5e19..5de93f2 100644
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -179,7 +179,7 @@ void sim_t::make_device_tree()
         dt.begin_node(buf);
           dt.add_prop("device_type", "cpu");
           dt.add_prop("compatible", "riscv");
-          dt.add_prop("isa", procs[i]->isa);
+          dt.add_prop("isa", procs[i]->isa_string);
           dt.add_reg({cpu_addr});
         dt.end_node();