From: Florent Kermarrec Date: Tue, 13 Nov 2018 13:46:20 +0000 (+0100) Subject: cores/clock/S7: just reset the generated clock, not the PLL/MMCM X-Git-Tag: 24jan2021_ls180~1495 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b4bdf2a0233b1641316fe08ba30bb7d6fb12db01;p=litex.git cores/clock/S7: just reset the generated clock, not the PLL/MMCM --- diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py index c11dfb16..a4cbb633 100644 --- a/litex/soc/cores/clock.py +++ b/litex/soc/cores/clock.py @@ -138,7 +138,7 @@ class S7PLL(S7Clocking): config = self.compute_config() pll_fb = Signal() self.params.update( - p_STARTUP_WAIT="FALSE", i_RST=self.reset, o_LOCKED=self.locked, + p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked, # VCO p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=period_ns(self.clkin_freq), @@ -174,7 +174,7 @@ class S7MMCM(S7Clocking): config = self.compute_config() mmcm_fb = Signal() self.params.update( - p_BANDWIDTH="OPTIMIZED", i_RST=self.reset, o_LOCKED=self.locked, + p_BANDWIDTH="OPTIMIZED", o_LOCKED=self.locked, # VCO p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=period_ns(self.clkin_freq),