From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 21 May 2020 19:55:46 +0000 (+0100)
Subject: whitespace cleanup
X-Git-Tag: div_pipeline~963
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b4c273f89d2c562944f5d75334bd381565260845;p=soc.git

whitespace cleanup
---

diff --git a/src/soc/fu/cr/main_stage.py b/src/soc/fu/cr/main_stage.py
index 81ab6b70..98d10cfa 100644
--- a/src/soc/fu/cr/main_stage.py
+++ b/src/soc/fu/cr/main_stage.py
@@ -47,7 +47,6 @@ class CRMainStage(PipeModBase):
         mask = Signal(32, reset_less=True)
         comb += mask.eq(Cat(*[Repl(FXM[i], 4) for i in range(8)]))
 
-
         # Generate array of bits for cr_a and cr_b
         cr_a_arr = Array([cr_a[i] for i in range(4)])
         cr_b_arr = Array([cr_b[i] for i in range(4)])
@@ -55,7 +54,6 @@ class CRMainStage(PipeModBase):
 
         comb += cr_o.eq(cr_c)
 
-
         with m.Switch(op.insn_type):
             ##### mcrf #####
             with m.Case(InternalOp.OP_MCRF):
@@ -65,8 +63,6 @@ class CRMainStage(PipeModBase):
                 # cr, we don't have to do anything special
                 comb += cr_o.eq(cr_a)
 
-
-
             # ##### crand, cror, crnor etc. #####
             with m.Case(InternalOp.OP_CROP):
                 # crand/cror and friends get decoded to the same opcode, but
@@ -110,14 +106,12 @@ class CRMainStage(PipeModBase):
                 # insert the output bit into the 4-bit CR output
                 comb += cr_o_arr[bt].eq(bit_o)
 
-
             ##### mtcrf #####
             with m.Case(InternalOp.OP_MTCRF):
                 # mtocrf and mtcrf are essentially identical
                 # put input (RA) - mask-selected - into output CR, leave
                 # rest of CR alone.
-                comb += self.o.full_cr.eq((a[0:32] & mask) |
-                                          (self.i.full_cr & ~mask))
+                comb += self.o.full_cr.eq((a[0:32] & mask) | (full_cr & ~mask))
 
             # ##### mfcr #####
             with m.Case(InternalOp.OP_MFCR):
@@ -130,11 +124,11 @@ class CRMainStage(PipeModBase):
                 # mfocrf
                 with m.If(move_one):
                     # output register RT
-                    comb += self.o.o.eq(self.i.full_cr & mask) 
+                    comb += self.o.o.eq(full_cr & mask)
                 # mfcrf
                 with m.Else():
                     # output register RT
-                    comb += self.o.o.eq(self.i.full_cr)
+                    comb += self.o.o.eq(full_cr)
 
         comb += self.o.ctx.eq(self.i.ctx)