From: Segher Boessenkool Date: Sun, 21 Sep 2014 18:01:01 +0000 (+0200) Subject: rs6000.md (iorxor): New code_iterator. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b4e2da9e22fc9eb0a585951fe6a02d4b1ad0f4fe;p=gcc.git rs6000.md (iorxor): New code_iterator. 2014-09-21 Segher Boessenkool * config/rs6000/rs6000.md (iorxor): New code_iterator. (iorxor): New code_attr. (IORXOR): New code_attr. (*and3, *and3_dot, *and3_dot2): Delete. (ior3, xor3): Delete. (3): New. (splitter for "big" integer ior, xor): New. (*bool3): Move. Also handle AND. (*bool3_dot, *bool3_dot2): Also handle AND. (splitter for "big" integer ior, xor): Delete. From-SVN: r215433 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b3aa885c760..af1ebbc64a0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2014-09-21 Segher Boessenkool + + * config/rs6000/rs6000.md (iorxor): New code_iterator. + (iorxor): New code_attr. + (IORXOR): New code_attr. + (*and3, *and3_dot, *and3_dot2): Delete. + (ior3, xor3): Delete. + (3): New. + (splitter for "big" integer ior, xor): New. + (*bool3): Move. Also handle AND. + (*bool3_dot, *bool3_dot2): Also handle AND. + (splitter for "big" integer ior, xor): Delete. + 2014-09-21 Segher Boessenkool * config/rs6000/rs6000.md (*neg2_internal): Delete. diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 48cc73deb9e..b2f5c55534f 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -438,6 +438,11 @@ (simple_return "1")]) (define_code_attr return_str [(return "") (simple_return "simple_")]) +; Logical operators. +(define_code_iterator iorxor [ior xor]) +(define_code_attr iorxor [(ior "ior") (xor "xor")]) +(define_code_attr IORXOR [(ior "IOR") (xor "XOR")]) + ; Signed/unsigned variants of ops. (define_code_iterator any_extend [sign_extend zero_extend]) (define_code_attr u [(sign_extend "") (zero_extend "u")]) @@ -2640,61 +2645,6 @@ }) -(define_insn "*and3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") - (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") - (match_operand:GPR 2 "gpc_reg_operand" "r")))] - "" - "and %0,%1,%2" - [(set_attr "type" "logical")]) - -(define_insn_and_split "*and3_dot" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") - (match_operand:GPR 2 "gpc_reg_operand" "r,r")) - (const_int 0))) - (clobber (match_scratch:GPR 0 "=r,r"))] - "mode == Pmode && rs6000_gen_cell_microcode" - "@ - and. %0,%1,%2 - #" - "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)" - [(set (match_dup 0) - (and:GPR (match_dup 1) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "" - [(set_attr "type" "logical") - (set_attr "dot" "yes") - (set_attr "length" "4,8")]) - -(define_insn_and_split "*and3_dot2" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") - (match_operand:GPR 2 "gpc_reg_operand" "r,r")) - (const_int 0))) - (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") - (and:GPR (match_dup 1) - (match_dup 2)))] - "mode == Pmode && rs6000_gen_cell_microcode" - "@ - and. %0,%1,%2 - #" - "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)" - [(set (match_dup 0) - (and:GPR (match_dup 1) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "" - [(set_attr "type" "logical") - (set_attr "dot" "yes") - (set_attr "length" "4,8")]) - - (define_insn "and3_imm" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r") @@ -2913,15 +2863,15 @@ [(set_attr "length" "8")]) -(define_expand "ior3" +(define_expand "3" [(set (match_operand:SDI 0 "gpc_reg_operand" "") - (ior:SDI (match_operand:SDI 1 "gpc_reg_operand" "") - (match_operand:SDI 2 "reg_or_cint_operand" "")))] + (iorxor:SDI (match_operand:SDI 1 "gpc_reg_operand" "") + (match_operand:SDI 2 "reg_or_cint_operand" "")))] "" { if (mode == DImode && !TARGET_POWERPC64) { - rs6000_split_logical (operands, IOR, false, false, false); + rs6000_split_logical (operands, , false, false, false); DONE; } @@ -2930,12 +2880,13 @@ rtx tmp = ((!can_create_pseudo_p () || rtx_equal_p (operands[0], operands[1])) ? operands[0] : gen_reg_rtx (mode)); - HOST_WIDE_INT value = INTVAL (operands[2]); - emit_insn (gen_ior3 (tmp, operands[1], - GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); + HOST_WIDE_INT value = INTVAL (operands[2]); + HOST_WIDE_INT lo = value & 0xffff; + HOST_WIDE_INT hi = value - lo; - emit_insn (gen_ior3 (operands[0], tmp, GEN_INT (value & 0xffff))); + emit_insn (gen_3 (tmp, operands[1], GEN_INT (hi))); + emit_insn (gen_3 (operands[0], tmp, GEN_INT (lo))); DONE; } @@ -2943,45 +2894,30 @@ operands[2] = force_reg (mode, operands[2]); }) -(define_expand "xor3" - [(set (match_operand:SDI 0 "gpc_reg_operand" "") - (xor:SDI (match_operand:SDI 1 "gpc_reg_operand" "") - (match_operand:SDI 2 "reg_or_cint_operand" "")))] +(define_split + [(set (match_operand:GPR 0 "gpc_reg_operand" "") + (iorxor:GPR (match_operand:GPR 1 "gpc_reg_operand" "") + (match_operand:GPR 2 "non_logical_cint_operand" "")))] "" + [(set (match_dup 3) + (iorxor:GPR (match_dup 1) + (match_dup 4))) + (set (match_dup 0) + (iorxor:GPR (match_dup 3) + (match_dup 5)))] { - if (mode == DImode && !TARGET_POWERPC64) - { - rs6000_split_logical (operands, XOR, false, false, false); - DONE; - } - - if (non_logical_cint_operand (operands[2], mode)) - { - rtx tmp = ((!can_create_pseudo_p () + operands[3] = ((!can_create_pseudo_p () || rtx_equal_p (operands[0], operands[1])) ? operands[0] : gen_reg_rtx (mode)); - HOST_WIDE_INT value = INTVAL (operands[2]); - - emit_insn (gen_xor3 (tmp, operands[1], - GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); - emit_insn (gen_xor3 (operands[0], tmp, GEN_INT (value & 0xffff))); - DONE; - } + HOST_WIDE_INT value = INTVAL (operands[2]); + HOST_WIDE_INT lo = value & 0xffff; + HOST_WIDE_INT hi = value - lo; - if (!reg_or_logical_cint_operand (operands[2], mode)) - operands[2] = force_reg (mode, operands[2]); + operands[4] = GEN_INT (hi); + operands[5] = GEN_INT (lo); }) -(define_insn "*bool3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") - (match_operator:GPR 3 "boolean_or_operator" - [(match_operand:GPR 1 "gpc_reg_operand" "r") - (match_operand:GPR 2 "gpc_reg_operand" "r")]))] - "" - "%q3 %0,%1,%2" - [(set_attr "type" "logical")]) - (define_insn "*bool3_imm" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (match_operator:GPR 3 "boolean_or_operator" @@ -2991,9 +2927,18 @@ "%q3i%e2 %0,%1,%u2" [(set_attr "type" "logical")]) +(define_insn "*bool3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (match_operator:GPR 3 "boolean_operator" + [(match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:GPR 2 "gpc_reg_operand" "r")]))] + "" + "%q3 %0,%1,%2" + [(set_attr "type" "logical")]) + (define_insn_and_split "*bool3_dot" [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") - (compare:CC (match_operator:GPR 3 "boolean_or_operator" + (compare:CC (match_operator:GPR 3 "boolean_operator" [(match_operand:GPR 1 "gpc_reg_operand" "r,r") (match_operand:GPR 2 "gpc_reg_operand" "r,r")]) (const_int 0))) @@ -3015,7 +2960,7 @@ (define_insn_and_split "*bool3_dot2" [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") - (compare:CC (match_operator:GPR 3 "boolean_or_operator" + (compare:CC (match_operator:GPR 3 "boolean_operator" [(match_operand:GPR 1 "gpc_reg_operand" "r,r") (match_operand:GPR 2 "gpc_reg_operand" "r,r")]) (const_int 0))) @@ -3036,27 +2981,6 @@ (set_attr "dot" "yes") (set_attr "length" "4,8")]) -;; Split a logical operation that we can't do in one insn into two insns, -;; each of which does one 16-bit part. This is used by combine. - -(define_split - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (match_operator:GPR 3 "boolean_or_operator" - [(match_operand:GPR 1 "gpc_reg_operand" "") - (match_operand:GPR 2 "non_logical_cint_operand" "")]))] - "" - [(set (match_dup 0) (match_dup 4)) - (set (match_dup 0) (match_dup 5))] -{ - rtx i; - i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); - operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), mode, - operands[1], i); - i = GEN_INT (INTVAL (operands[2]) & 0xffff); - operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), mode, - operands[0], i); -}) - (define_insn "*boolc3" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")