From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 27 Jan 2021 12:38:35 +0000 (+0000)
Subject: move SVP64RM CSV class to new module
X-Git-Tag: convert-csv-opcode-to-binary~308
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b4e7b078e09220acd49bbaa84c1280630b7d10e4;p=soc.git

move SVP64RM CSV class to new module
---

diff --git a/src/soc/decoder/power_svp64.py b/src/soc/decoder/power_svp64.py
new file mode 100644
index 00000000..b7c7cde1
--- /dev/null
+++ b/src/soc/decoder/power_svp64.py
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: LGPLv3+
+# Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+# Funded by NLnet http://nlnet.nl
+
+from soc.decoder.power_enums import get_csv, find_wiki_dir
+import os
+
+# gets SVP64 ReMap information
+class SVP64RM:
+    def __init__(self):
+        self.instrs = {}
+        pth = find_wiki_dir()
+        for fname in os.listdir(pth):
+            if fname.startswith("RM") or fname.startswith("LDSTRM"):
+                for entry in get_csv(fname):
+                    self.instrs[entry['insn']] = entry
+
+
+
diff --git a/src/soc/sv/trans/svp64.py b/src/soc/sv/trans/svp64.py
index 0cb14a78..2e54f708 100644
--- a/src/soc/sv/trans/svp64.py
+++ b/src/soc/sv/trans/svp64.py
@@ -18,7 +18,7 @@ import os, sys
 from collections import OrderedDict
 
 from soc.decoder.pseudo.pagereader import ISA
-from soc.decoder.power_enums import get_csv, find_wiki_dir
+from soc.decoder.power_svp64 import SVP64RM
 
 
 # identifies register by type
@@ -129,16 +129,6 @@ def decode_ffirst(encoding):
     return decode_bo(encoding)
 
 
-# gets SVP64 ReMap information
-class SVP64RM:
-    def __init__(self):
-        self.instrs = {}
-        pth = find_wiki_dir()
-        for fname in os.listdir(pth):
-            if fname.startswith("RM") or fname.startswith("LDSTRM"):
-                for entry in get_csv(fname):
-                    self.instrs[entry['insn']] = entry
-
 
 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
 class SVP64: