From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 29 Mar 2023 16:00:16 +0000 (+0100)
Subject: add page-boundaries to ls010
X-Git-Tag: opf_rfc_ls012_v1~248
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b4f43f7a1e6ab9f73994affec572793e98402a61;p=libreriscv.git

add page-boundaries to ls010
---

diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn
index c9a6e1bdd..264b096a2 100644
--- a/openpower/sv/rfc/ls010.mdwn
+++ b/openpower/sv/rfc/ls010.mdwn
@@ -209,6 +209,10 @@ RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers.  This is
 With the way that EXTRA fields are defined and applied to register fields,
 future versions of SV may involve 256 or greater registers. Backwards binary compatibility may be achieved with a PCR bit (Program Compatibility Register).  Further discussion is out of scope for this version of SVP64.
 
+--------
+
+\newpage{}
+
 # Remapped Encoding (`RM[0:23]`)
 
 To allow relatively easy remapping of which portions of the Prefix Opcode
@@ -727,6 +731,10 @@ For a 3-bit operand (e.g. BFA):
 | 10    | Vector | `CR0-CR112`/16 | BFA 0 | 0b000   |
 | 11    | Vector | `CR8-CR120`/16 | BFA 1 | 0b000   |
 
+--------
+
+\newpage{}
+
 
 # Normal SVP64 Modes, for Arithmetic and Logical Operations
 
@@ -789,11 +797,9 @@ For LD/ST Modes, see [[sv/ldst]].  For Condition Registers
 see [[sv/cr_ops]].
 For Branch modes, see [[sv/branches]].
 
-# Rounding, clamp and saturate
+## Rounding, clamp and saturate
 
-See [[av_opcodes]] for relevant opcodes and use-cases.
-
-To help ensure that audio quality is not compromised by overflow,
+To help ensure for example that audio quality is not compromised by overflow,
 "saturation" is provided, as well as a way to detect when saturation
 occurred if desired (Rc=1). When Rc=1 there will be a *vector* of CRs,
 one CR per element in the result (Note: this is different from VSX which
@@ -994,6 +1000,10 @@ element result is *always* discarded, never written (just like `cmp`).
 Note that predication is still respected: predicate zeroing is slightly
 different: elements that fail the CR test *or* are masked out are zero'd.
 
+--------
+
+\newpage{}
+
 # SV Load and Store
 
 **Rationale**
@@ -1071,7 +1081,7 @@ to lack of space, have the following quirks:
 * LD/ST Immediate has no Saturated Pack/Unpack (Arithmetic Mode does)
 * LD/ST Indexed has no Pack/Unpack (REMAP may be used instead)
 
-# Format and fields
+## Format and fields
 
 Fields used in tables below:
 
@@ -1554,7 +1564,7 @@ for clarity: predication and all modes except saturation are removed:
         j++;
 ```
 
-# Remapped LD/ST
+## Remapped LD/ST
 
 In the [[sv/remap]] page the concept of "Remapping" is described.
 Whilst it is expensive to set up (2 64-bit opcodes minimum) it provides
@@ -1577,6 +1587,10 @@ established through `svstep`, are also an easy way to perform regular
 Structure Packing, at the vec2/vec3/vec4 granularity level.  Beyond
 that, REMAP will need to be used.
 
+--------
+
+\newpage{}
+
 # Condition Register SVP64 Operations
 
 Condition Register Fields are only 4 bits wide: this presents some
@@ -1801,7 +1815,11 @@ treat *individual bits* of a GPR effectively as elements.  They are
 expected to be Micro-coded by most Hardware implementations.
 
 
-## SVP64 Branch Conditional behaviour
+--------
+
+\newpage{}
+
+# SVP64 Branch Conditional behaviour
 
 Please note: although similar, SVP64 Branch instructions should be
 considered completely separate and distinct from
@@ -2628,3 +2646,5 @@ as such is not at all appropriate:
     # which is clearly impossible
     if LK then LR <-iea CIA + 4
 ```
+
+[[!tag standards]]