From: Andrey Miroshnikov <andrey@technepisteme.xyz>
Date: Thu, 3 Aug 2023 13:16:00 +0000 (+0000)
Subject: gen_core_with_svp64: Fixed make command
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b5086c72247de1a02b129fa101bbfead502edc9e;p=libreriscv.git

gen_core_with_svp64: Fixed make command
---

diff --git a/HDL_workflow/gen_core_with_svp64.mdwn b/HDL_workflow/gen_core_with_svp64.mdwn
index 36579cf43..888e6f891 100644
--- a/HDL_workflow/gen_core_with_svp64.mdwn
+++ b/HDL_workflow/gen_core_with_svp64.mdwn
@@ -65,7 +65,7 @@ see [Bug #1127 comment #0](https://bugs.libre-soc.org/show_bug.cgi?id=1127#c0)
     (gen_cores):$ make pywriter
     (gen_cores):$ make pyfnwriter
     (gen_cores):$ cd ../soc/
-    (gen_cores):$ make microwatt_external_core
+    (gen_cores):$ make microwatt_external_core_svp64
 
 At this point you should end up with `external_core_top.v` verilog file, which
 contains the Libre-SOC core (with Microwatt-compatible interfaces).