From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 25 Mar 2020 18:07:06 +0000 (+0100)
Subject: integration/soc/add_uart: add USB CDC support (with ValentyUSB core).
X-Git-Tag: 24jan2021_ls180~515
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b509df8bb6ecb7d9fb81592c6f12f251ecb24afc;p=litex.git

integration/soc/add_uart: add USB CDC support (with ValentyUSB core).
---

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 53684fdf..fb2bfb74 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -954,6 +954,14 @@ class LiteXSoC(SoC):
                 tx_fifo_depth = fifo_depth,
                 rx_fifo_depth = fifo_depth))
 
+        # USB CDC (with ValentyUSB core)
+        elif name in ["usb_cdc"]:
+            import valentyusb.usbcore.io as usbio
+            import valentyusb.usbcore.cpu.cdc_eptri as cdc_eptri
+            usb_pads = self.platform.request("usb")
+            usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
+            self.submodules.uart = cdc_eptri.CDCUsb(usb_iobuf)
+
         # Classic UART
         else:
             self.submodules.uart_phy = uart.UARTPHY(