From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Sun, 8 May 2016 04:14:18 +0000 (-0700)
Subject: Fixed extra semicolon
X-Git-Tag: yosys-0.7~226^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b5171541cd9da6a4e2b5aaaaf3bca76e059c7e3f;p=yosys.git

Fixed extra semicolon
---

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index c4e5a9de1..5a59a06b4 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -1,4 +1,4 @@
-`timescale 1ns/1ps;
+`timescale 1ns/1ps
 
 module GP_2LUT(input IN0, IN1, output OUT);
 	parameter [3:0] INIT = 0;