From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 24 Apr 2020 18:57:55 +0000 (-0700)
Subject: Revert "verific: import enum attributes from verific"
X-Git-Tag: working-ls180~581^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b52eccef3a40116c035e91eff5df80134b310db4;p=yosys.git

Revert "verific: import enum attributes from verific"

This reverts commit 5028e17f7db11f901ce9e423dfe2c6f7e68259cc.
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 89606a5bd..519151310 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1153,30 +1153,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 	for (auto net : anyseq_nets)
 		module->connect(net_map_at(net), module->Anyseq(new_verific_id(net)));
 
-	char *id_name;
-	TypeRange *type_range;
-	FOREACH_MAP_ITEM(nl->GetTypeRangeTable(), mi, &id_name, &type_range)
-	{
-		if (!type_range)
-			continue;
-		if (!type_range->IsTypeEnum())
-			continue;
-		auto wire = module->wire(RTLIL::escape_id(id_name));
-		if (!wire) {
-			if (net->IsUserDeclared())
-				log_warning("Unable to find imported net '%s'.\n", net->Name());
-			continue;
-		}
-		wire->set_string_attribute(ID::wiretype, type_range->GetTypeName());
-
-		MapIter mj;
-		char *k, *v;
-		FOREACH_MAP_ITEM(type_range->GetEnumIdMap(), mj, &k, &v) {
-			IdString key = stringf("\\enum_value_%s", v);
-			wire->set_string_attribute(key, k);
-		}
-	}
-
 	pool<Instance*, hash_ptr_ops> sva_asserts;
 	pool<Instance*, hash_ptr_ops> sva_assumes;
 	pool<Instance*, hash_ptr_ops> sva_covers;