From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sat, 2 Apr 2022 08:33:41 +0000 (+0200)
Subject: Set past_d value for init state
X-Git-Tag: yosys-0.16~4^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b54aecd80a58dc2a7f5069ee03561d64efdba765;p=yosys.git

Set past_d value for init state
---

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 65bd5c78e..d74fbcc4e 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -782,6 +782,7 @@ struct SimInstance
 	{
 		for (auto &it : ff_database)
 		{
+			ff_state_t &ff = it.second;
 			SigSpec qsig = it.second.data.sig_q;
 			if (qsig.is_wire()) {
 				IdString name = qsig.as_wire()->name;
@@ -790,6 +791,7 @@ struct SimInstance
 					log_warning("Unable to find wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(name)).c_str());
 				if (id!=0) {
 					Const fst_val = Const::from_string(shared->fst->valueOf(id));
+					ff.past_d = fst_val;
 					set_state(qsig, fst_val);
 				}
 			}