From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 5 Dec 2021 01:07:50 +0000 (+0000)
Subject: connect to dcache.bus standard interface when using wb_get
X-Git-Tag: sv_maxu_works-initial~662
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b5529992131d76d1d866358faaeb6c0fb2105851;p=openpower-isa.git

connect to dcache.bus standard interface when using wb_get
---

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index 51f4a596..2d6a825e 100644
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -461,7 +461,8 @@ class TestRunnerBase(FHDLTestCase):
         if self.rom is not None:
             dcache = hdlrun.issuer.core.fus.fus["mmu0"].alu.dcache
             default_mem = self.rom
-            sim.add_sync_process(wrap(wb_get(dcache, default_mem, "DCACHE")))
+            sim.add_sync_process(wrap(wb_get(dcache.bus,
+                                             default_mem, "DCACHE")))
 
         with sim.write_vcd("issuer_simulator.vcd"):
             sim.run()