From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Mon, 24 Jun 2013 17:44:25 +0000 (+0200)
Subject: fhdl/verilog: improve error reporting
X-Git-Tag: 24jan2021_ls180~2099^2~552
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b56cb3cefc2e46e8316de37abf1cdd3de7d1ee9b;p=litex.git

fhdl/verilog: improve error reporting
---

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 66c28799..8dc404fe 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -80,7 +80,7 @@ def _printexpr(ns, node):
 	elif isinstance(node, Replicate):
 		return "{" + str(node.n) + "{" + _printexpr(ns, node.v)[0] + "}}", False
 	else:
-		raise TypeError
+		raise TypeError("Expression of unrecognized type: "+str(type(node)))
 
 (_AT_BLOCKING, _AT_NONBLOCKING, _AT_SIGNAL) = range(3)
 
@@ -124,7 +124,7 @@ def _printnode(ns, at, level, node):
 		else:
 			return ""
 	else:
-		raise TypeError
+		raise TypeError("Node of unrecognized type: "+str(type(node)))
 
 def _list_comb_wires(f):
 	r = set()