From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 7 May 2013 12:35:40 +0000 (+0200)
Subject: Added support for verilog === operator
X-Git-Tag: yosys-0.2.0~638
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b56e06d2f518b79481309636c57fa40500d425e8;p=yosys.git

Added support for verilog === operator
---

diff --git a/frontends/verilog/lexer.l b/frontends/verilog/lexer.l
index 2a6c44171..f899191bb 100644
--- a/frontends/verilog/lexer.l
+++ b/frontends/verilog/lexer.l
@@ -233,6 +233,8 @@ supply1 { return TOK_SUPPLY1; }
 "<=" { return OP_LE; }
 ">=" { return OP_GE; }
 
+"===" { return OP_EQ; }
+
  /* "~&" { return OP_NAND; } */
  /* "~|" { return OP_NOR;  } */
 "~^" { return OP_XNOR; }