From: Alexander Ivchenko Date: Mon, 15 Sep 2014 11:36:54 +0000 (+0000) Subject: AVX-512. Extend vcvtps2ph insn patterns. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b570c6dd40c3c4d11bcb387140a3c97abaa84ab1;p=gcc.git AVX-512. Extend vcvtps2ph insn patterns. gcc/ * config/i386/sse.md (define_insn "vcvtph2ps"): Add masking. (define_insn "*vcvtph2ps_load"): Ditto. (define_insn "vcvtph2ps256"): Ditto. (define_expand "vcvtps2ph_mask"): New. (define_insn "*vcvtps2ph"): Add masking. (define_insn "*vcvtps2ph_store"): Ditto. (define_insn "vcvtps2ph256"): Ditto. Co-Authored-By: Andrey Turetskiy Co-Authored-By: Anna Tikhonova Co-Authored-By: Ilya Tocar Co-Authored-By: Ilya Verbin Co-Authored-By: Kirill Yukhin Co-Authored-By: Maxim Kuznetsov Co-Authored-By: Michael Zolotukhin From-SVN: r215263 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 920e98f2b02..dfb70506e2c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,21 @@ +2014-09-15 Alexander Ivchenko + Maxim Kuznetsov + Anna Tikhonova + Ilya Tocar + Andrey Turetskiy + Ilya Verbin + Kirill Yukhin + Michael Zolotukhin + + * config/i386/sse.md + (define_insn "vcvtph2ps"): Add masking. + (define_insn "*vcvtph2ps_load"): Ditto. + (define_insn "vcvtph2ps256"): Ditto. + (define_expand "vcvtps2ph_mask"): New. + (define_insn "*vcvtps2ph"): Add masking. + (define_insn "*vcvtps2ph_store"): Ditto. + (define_insn "vcvtps2ph256"): Ditto. + 2014-09-15 Alexander Ivchenko Maxim Kuznetsov Anna Tikhonova diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index b5ded79a0e8..bd321fcefc0 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -16423,35 +16423,35 @@ (set_attr "prefix" "maybe_evex") (set_attr "mode" "")]) -(define_insn "vcvtph2ps" - [(set (match_operand:V4SF 0 "register_operand" "=x") +(define_insn "vcvtph2ps" + [(set (match_operand:V4SF 0 "register_operand" "=v") (vec_select:V4SF - (unspec:V8SF [(match_operand:V8HI 1 "register_operand" "x")] + (unspec:V8SF [(match_operand:V8HI 1 "register_operand" "v")] UNSPEC_VCVTPH2PS) (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)])))] - "TARGET_F16C" - "vcvtph2ps\t{%1, %0|%0, %1}" + "TARGET_F16C || TARGET_AVX512VL" + "vcvtph2ps\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") - (set_attr "prefix" "vex") + (set_attr "prefix" "maybe_evex") (set_attr "mode" "V4SF")]) -(define_insn "*vcvtph2ps_load" - [(set (match_operand:V4SF 0 "register_operand" "=x") +(define_insn "*vcvtph2ps_load" + [(set (match_operand:V4SF 0 "register_operand" "=v") (unspec:V4SF [(match_operand:V4HI 1 "memory_operand" "m")] UNSPEC_VCVTPH2PS))] - "TARGET_F16C" - "vcvtph2ps\t{%1, %0|%0, %1}" + "TARGET_F16C || TARGET_AVX512VL" + "vcvtph2ps\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "vex") (set_attr "mode" "V8SF")]) -(define_insn "vcvtph2ps256" - [(set (match_operand:V8SF 0 "register_operand" "=x") - (unspec:V8SF [(match_operand:V8HI 1 "nonimmediate_operand" "xm")] +(define_insn "vcvtph2ps256" + [(set (match_operand:V8SF 0 "register_operand" "=v") + (unspec:V8SF [(match_operand:V8HI 1 "nonimmediate_operand" "vm")] UNSPEC_VCVTPH2PS))] - "TARGET_F16C" - "vcvtph2ps\t{%1, %0|%0, %1}" + "TARGET_F16C || TARGET_AVX512VL" + "vcvtph2ps\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "vex") (set_attr "btver2_decode" "double") @@ -16468,6 +16468,19 @@ (set_attr "prefix" "evex") (set_attr "mode" "V16SF")]) +(define_expand "vcvtps2ph_mask" + [(set (match_operand:V8HI 0 "register_operand") + (vec_merge:V8HI + (vec_concat:V8HI + (unspec:V4HI [(match_operand:V4SF 1 "register_operand") + (match_operand:SI 2 "const_0_to_255_operand")] + UNSPEC_VCVTPS2PH) + (match_dup 5)) + (match_operand:V8HI 3 "vector_move_operand") + (match_operand:QI 4 "register_operand")))] + "TARGET_AVX512VL" + "operands[5] = CONST0_RTX (V4HImode);") + (define_expand "vcvtps2ph" [(set (match_operand:V8HI 0 "register_operand") (vec_concat:V8HI @@ -16478,39 +16491,39 @@ "TARGET_F16C" "operands[3] = CONST0_RTX (V4HImode);") -(define_insn "*vcvtps2ph" - [(set (match_operand:V8HI 0 "register_operand" "=x") +(define_insn "*vcvtps2ph" + [(set (match_operand:V8HI 0 "register_operand" "=v") (vec_concat:V8HI - (unspec:V4HI [(match_operand:V4SF 1 "register_operand" "x") + (unspec:V4HI [(match_operand:V4SF 1 "register_operand" "v") (match_operand:SI 2 "const_0_to_255_operand" "N")] UNSPEC_VCVTPS2PH) (match_operand:V4HI 3 "const0_operand")))] - "TARGET_F16C" - "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}" + "TARGET_F16C && " + "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ssecvt") - (set_attr "prefix" "vex") + (set_attr "prefix" "maybe_evex") (set_attr "mode" "V4SF")]) -(define_insn "*vcvtps2ph_store" +(define_insn "*vcvtps2ph_store" [(set (match_operand:V4HI 0 "memory_operand" "=m") (unspec:V4HI [(match_operand:V4SF 1 "register_operand" "x") (match_operand:SI 2 "const_0_to_255_operand" "N")] UNSPEC_VCVTPS2PH))] - "TARGET_F16C" - "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}" + "TARGET_F16C || TARGET_AVX512VL" + "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ssecvt") - (set_attr "prefix" "vex") + (set_attr "prefix" "maybe_evex") (set_attr "mode" "V4SF")]) -(define_insn "vcvtps2ph256" +(define_insn "vcvtps2ph256" [(set (match_operand:V8HI 0 "nonimmediate_operand" "=xm") (unspec:V8HI [(match_operand:V8SF 1 "register_operand" "x") (match_operand:SI 2 "const_0_to_255_operand" "N")] UNSPEC_VCVTPS2PH))] - "TARGET_F16C" - "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}" + "TARGET_F16C || TARGET_AVX512VL" + "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ssecvt") - (set_attr "prefix" "vex") + (set_attr "prefix" "maybe_evex") (set_attr "btver2_decode" "vector") (set_attr "mode" "V8SF")])