From: Anton Blanchard <anton@linux.ibm.com>
Date: Tue, 24 Sep 2019 07:33:21 +0000 (+1000)
Subject: Merge branch 'divider' of https://github.com/paulusmack/microwatt
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b57325ce294beab5a07aee59af8aad7e09485ff8;p=microwatt.git

Merge branch 'divider' of https://github.com/paulusmack/microwatt
---

b57325ce294beab5a07aee59af8aad7e09485ff8
diff --cc Makefile
index 0649f45,318866d..ddf35c3
--- a/Makefile
+++ b/Makefile
@@@ -1,9 -1,8 +1,9 @@@
  GHDL=ghdl
 -GHDLFLAGS=--std=08
 +GHDLFLAGS=--std=08 -Psim-unisim
  CFLAGS=-O2 -Wall
  
- all = core_tb simple_ram_behavioural_tb soc_reset_tb icache_tb multiply_tb dmi_dtm_tb
 -all = core_tb simple_ram_behavioural_tb soc_reset_tb icache_tb multiply_tb divider_tb
++all = core_tb simple_ram_behavioural_tb soc_reset_tb icache_tb multiply_tb dmi_dtm_tb divider_tb
 +
  # XXX
  # loadstore_tb fetch_tb
  
@@@ -13,10 -12,8 +13,10 @@@ all: $(all
  	$(GHDL) -a $(GHDLFLAGS) $<
  
  common.o: decode_types.o
 -core_tb.o: common.o core.o soc.o
 -core.o: common.o wishbone_types.o fetch1.o fetch2.o icache.o decode1.o decode2.o register_file.o cr_file.o execute1.o execute2.o loadstore1.o loadstore2.o multiply.o divider.o writeback.o
 +sim_jtag.o: sim_jtag_socket.o
 +core_tb.o: common.o core.o soc.o sim_jtag.o
- core.o: common.o wishbone_types.o fetch1.o fetch2.o icache.o decode1.o decode2.o register_file.o cr_file.o execute1.o execute2.o loadstore1.o loadstore2.o multiply.o writeback.o core_debug.o
++core.o: common.o wishbone_types.o fetch1.o fetch2.o icache.o decode1.o decode2.o register_file.o cr_file.o execute1.o execute2.o loadstore1.o loadstore2.o multiply.o writeback.o core_debug.o divider.o
 +core_debug.o:
  cr_file.o: common.o
  crhelpers.o: common.o
  decode1.o: common.o decode_types.o
diff --cc microwatt.core
index 2bc428c,c2020a4..856c694
--- a/microwatt.core
+++ b/microwatt.core
@@@ -23,12 -23,11 +23,13 @@@ filesets
        - loadstore1.vhdl
        - loadstore2.vhdl
        - multiply.vhdl
+       - divider.vhdl
        - writeback.vhdl
        - insn_helpers.vhdl
 +      - wishbone_debug_master.vhdl
        - core.vhdl
        - icache.vhdl
 +      - core_debug.vhdl
      file_type : vhdlSource-2008
  
    soc: