From: Xiretza <xiretza@xiretza.xyz>
Date: Thu, 18 Mar 2021 09:38:36 +0000 (+0100)
Subject: verilog: fix wildcard port connections leaking memory
X-Git-Tag: yosys-0.10~134
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b57e47fad8b4ecd5438ee49c618fc8978a4bb058;p=yosys.git

verilog: fix wildcard port connections leaking memory
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 4e601b51d..7d750ea28 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -2084,6 +2084,7 @@ cell_port:
 		if (!sv_mode)
 			frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode.");
 		astbuf2->attributes[ID::wildcard_port_conns] = AstNode::mkconst_int(1, false);
+		free_attr($1);
 	};
 
 always_comb_or_latch: