From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 3 Jun 2021 14:42:32 +0000 (+0100)
Subject: rename ref to ref_v in PLL due to ref being a verilog keyword
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b580c7703fb09fff550ba13c56368ed9b3d097e0;p=soc.git

rename ref to ref_v in PLL due to ref being a verilog keyword
---

diff --git a/src/soc/clock/dummypll.py b/src/soc/clock/dummypll.py
index 2363274c..1fcc4f3b 100644
--- a/src/soc/clock/dummypll.py
+++ b/src/soc/clock/dummypll.py
@@ -22,7 +22,7 @@ class DummyPLL(Elaboratable):
             clk_pll_o = Signal(reset_less=True)  # output clock
             pll_test_o = Signal(reset_less=True)  # test out
             pll_vco_o = Signal(reset_less=True) # analog
-            pll = Instance("pll", i_ref=clk_24_i,
+            pll = Instance("pll", i_ref_v=clk_24_i,
                                   i_a0=clk_sel_i[0],
                                   i_a1=clk_sel_i[1],
                                   o_out_v=clk_pll_o,