From: Bobby R. Bruce <bbruce@ucdavis.edu>
Date: Tue, 15 Sep 2020 03:29:24 +0000 (-0700)
Subject: cpu,misc: Revert problematic terminology renames in BaseCPU
X-Git-Tag: v20.1.0.0~26
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b5850b69d1bad721b04344f19de69097040f8b91;p=gem5.git

cpu,misc: Revert problematic terminology renames in BaseCPU

Due to gem5's use of duck-typing, we must termorarly revert the
terminology in BaseCPU back to master/slave to avoid issues.

This fixes https://gem5.atlassian.net/browse/GEM5-775.

Change-Id: Idf1cb99aa9568ee70943ebec96f27394d8167f8c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34495
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index c9e8ae6a6..ad91f3a53 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -194,13 +194,13 @@ class BaseCPU(ClockedObject):
 
     def connectCachedPorts(self, bus):
         for p in self._cached_ports:
-            exec('self.%s = bus.cpu_side_ports' % p)
+            exec('self.%s = bus.slave' % p)
 
     def connectUncachedPorts(self, bus):
         for p in self._uncached_interrupt_response_ports:
-            exec('self.%s = bus.mem_side_ports' % p)
+            exec('self.%s = bus.master' % p)
         for p in self._uncached_interrupt_request_ports:
-            exec('self.%s = bus.cpu_side_ports' % p)
+            exec('self.%s = bus.slave' % p)
 
     def connectAllPorts(self, cached_bus, uncached_bus = None):
         self.connectCachedPorts(cached_bus)