From: Tobias Platen <tplaten@posteo.de>
Date: Mon, 20 Apr 2020 15:04:33 +0000 (+0200)
Subject: testcase for addis
X-Git-Tag: div_pipeline~1419
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b58daa5f09d736173c0aa531fe8a7abad9ae5db1;p=soc.git

testcase for addis
---

diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index c170397e..f356dd76 100644
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -108,6 +108,13 @@ class DecoderTestCase(FHDLTestCase):
         with Program(lst) as program:
             self.run_tst_program(program, [1, 2, 3])
 
+    def test_addis(self):
+        lst = ["addi 1, 0, 0x0FFF",
+               "addis 1, 1, 0x0F"
+               ]
+        with Program(lst) as program:
+            self.run_tst_program(program, [1])
+
     def run_tst_program(self, prog, reglist):
         simulator = InternalOpSimulator()
         self.run_tst(prog, simulator)