From: Claire Wolf Date: Tue, 3 Mar 2020 16:38:32 +0000 (-0800) Subject: Merge pull request #1718 from boqwxp/precise_locations X-Git-Tag: working-ls180~776 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b597f85b13b5369398350ef4ef43b7b2521eb140;p=yosys.git Merge pull request #1718 from boqwxp/precise_locations Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes. --- b597f85b13b5369398350ef4ef43b7b2521eb140 diff --cc frontends/ast/simplify.cc index 9a8150ebf,2c61f65f4..04c02d893 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@@ -1322,25 -1320,19 +1320,25 @@@ bool AstNode::simplify(bool const_fold } if (varbuf->type != AST_CONSTANT) - log_file_error(filename, linenum, "Right hand side of 1st expression of generate for-loop is not constant!\n"); + log_file_error(filename, location.first_line, "Right hand side of 1st expression of generate for-loop is not constant!\n"); - varbuf = new AstNode(AST_LOCALPARAM, varbuf); - varbuf->str = init_ast->children[0]->str; - auto resolved = current_scope.at(init_ast->children[0]->str); if (resolved->range_valid) { - varbuf->range_left = resolved->range_left; - varbuf->range_right = resolved->range_right; - varbuf->range_swapped = resolved->range_swapped; - varbuf->range_valid = resolved->range_valid; + int const_size = varbuf->range_left - varbuf->range_right; + int resolved_size = resolved->range_left - resolved->range_right; + if (const_size < resolved_size) { + for (int i = const_size; i < resolved_size; i++) + varbuf->bits.push_back(resolved->is_signed ? varbuf->bits.back() : State::S0); + varbuf->range_left = resolved->range_left; + varbuf->range_right = resolved->range_right; + varbuf->range_swapped = resolved->range_swapped; + varbuf->range_valid = resolved->range_valid; + } } + varbuf = new AstNode(AST_LOCALPARAM, varbuf); + varbuf->str = init_ast->children[0]->str; + AstNode *backup_scope_varbuf = current_scope[varbuf->str]; current_scope[varbuf->str] = varbuf;