From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 15 Jul 2020 16:42:05 +0000 (+0100)
Subject: simplify instr_is_priv
X-Git-Tag: div_pipeline~15
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b59a8ec56a89e1f148ab41499442d5c51aee6786;p=soc.git

simplify instr_is_priv
---

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 9f46e3f0..5abf8314 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -36,11 +36,9 @@ def instr_is_priv(m, op, insn):
     comb = m.d.comb
     is_priv_insn = Signal(reset_less=True)
     with m.Switch(op):
-        with m.Case(MicrOp.OP_ATTN)  : comb += is_priv_insn.eq(1)
-        with m.Case(MicrOp.OP_MFMSR) : comb += is_priv_insn.eq(1)
-        with m.Case(MicrOp.OP_MTMSRD): comb += is_priv_insn.eq(1)
-        with m.Case(MicrOp.OP_MTMSR): comb += is_priv_insn.eq(1)
-        with m.Case(MicrOp.OP_RFID)  : comb += is_priv_insn.eq(1)
+        with m.Case(MicrOp.OP_ATTN, MicrOp.OP_MFMSR, MicrOp.OP_MTMSRD,
+                    MicrOp.OP_MTMSR, MicrOp.OP_RFID):
+            comb += is_priv_insn.eq(1)
         # XXX TODO
         #with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
         with m.Case(MicrOp.OP_MFSPR, MicrOp.OP_MTSPR):