From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 31 Jan 2015 23:48:22 +0000 (+0100)
Subject: Removed TODO list from README file
X-Git-Tag: yosys-0.5~42
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b59bb8a528bf4fcf764016e61bf6a59239f35b86;p=yosys.git

Removed TODO list from README file
---

diff --git a/README b/README
index 942af4846..b7605eb59 100644
--- a/README
+++ b/README
@@ -366,33 +366,3 @@ from SystemVerilog:
 - The keywords "always_comb", "always_ff" and "always_latch", "logic" and
   "bit" are supported.
 
-
-Roadmap / Large-scale TODOs
-===========================
-
-- Technology mapping for real-world applications
-   - Improve Xilinx FGPA synthesis (RAMB, CARRY4, SLR, etc.)
-
-- Implement SAT-based formal equivialence checker
-   - Write equiv pass based on hint-based register mapping
-
-- Re-implement Verilog frontend (far future)
-   - cleaner (easier to use, harder to use wrong) AST format
-   - pipeline of well structured AST transformations
-   - true contextual name lookup
-
-
-Other Unsorted TODOs
-====================
-
-- Implement missing Verilog 2005 features:
-
-  - Support for real (float) const. expressions and parameters
-  - Ignore what needs to be ignored (e.g. drive and charge strengths)
-  - Check standard vs. implementation to identify missing features
-
-- Miscellaneous TODO items: 
-
-  - Add brief source code documentation to most passes and kernel code
-  - Implement mux-to-tribuf pass and rebalance mixed mux/tribuf trees
-