From: Anton Blanchard <anton@linux.ibm.com>
Date: Thu, 17 Mar 2022 07:03:29 +0000 (+1100)
Subject: wishbone_bram_wrapper ram_addr_bits is 1 bit off
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b5accb78b27c7cd8bfa4ec6dedf5d5c8069f8e5c;p=microwatt.git

wishbone_bram_wrapper ram_addr_bits is 1 bit off

log2ceil() returns the number of bits required to store a value, so we
need to pass in memory_size-1, not memory_size.

Every other user of log2ceil() gets this right.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
---

diff --git a/wishbone_bram_wrapper.vhdl b/wishbone_bram_wrapper.vhdl
index 182fd29..a45790f 100644
--- a/wishbone_bram_wrapper.vhdl
+++ b/wishbone_bram_wrapper.vhdl
@@ -24,7 +24,7 @@ entity wishbone_bram_wrapper is
 end entity wishbone_bram_wrapper;
 
 architecture behaviour of wishbone_bram_wrapper is
-    constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE) - 3;
+    constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE-1) - 3;
 
     -- RAM interface
     signal ram_addr : std_logic_vector(ram_addr_bits - 1 downto 0);