From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 4 Dec 2013 08:09:42 +0000 (+0100)
Subject: Fixed gentb_constant handling in autotest backend
X-Git-Tag: yosys-0.2.0~266
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b5afd75b0a8b620615bc53fa36d920760bdec46f;p=yosys.git

Fixed gentb_constant handling in autotest backend
---

diff --git a/backends/autotest/autotest.cc b/backends/autotest/autotest.cc
index 89ccc3718..3e2fab006 100644
--- a/backends/autotest/autotest.cc
+++ b/backends/autotest/autotest.cc
@@ -124,11 +124,11 @@ static void autotest(FILE *f, RTLIL::Design *design)
 							is_clksignal = true;
 					}
 				}
-				if (is_clksignal && !wire->get_bool_attribute("\\gentb_constant")) {
+				if (is_clksignal && wire->attributes.count("\\gentb_constant") == 0) {
 					signal_clk[idy("sig", mod->name, wire->name)] = wire->width;
 				} else {
 					signal_in[idy("sig", mod->name, wire->name)] = wire->width;
-					if (wire->get_bool_attribute("\\gentb_constant"))
+					if (wire->attributes.count("\\gentb_constant") != 0)
 						signal_const[idy("sig", mod->name, wire->name)] = wire->attributes["\\gentb_constant"].as_string();
 				}
 				fprintf(f, "reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name, wire->name).c_str());