From: Kenneth Graunke <kenneth@whitecape.org>
Date: Wed, 13 Feb 2013 05:51:17 +0000 (-0800)
Subject: i965/vs: Fix textureGrad() with shadow samplers on Haswell.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b5b6460c40e1c46f6af6a490485132ea0864572c;p=mesa.git

i965/vs: Fix textureGrad() with shadow samplers on Haswell.

The shadow comparitor needs to be loaded into the Z component of the
last DWord.

Fixes es3conform's shadow_execution_vert and oglconform's
shadow-grad advanced.textureGrad.1D tests on Haswell.

NOTE: This is a candidate for stable branches.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
---

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 31da01f143b..3b0687f615a 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -2271,7 +2271,7 @@ vec4_visitor::visit(ir_texture *ir)
       emit(MOV(dst_reg(MRF, param_base, ir->coordinate->type, zero_mask),
 	       src_reg(0)));
       /* Load the shadow comparitor */
-      if (ir->shadow_comparitor) {
+      if (ir->shadow_comparitor && ir->op != ir_txd) {
 	 emit(MOV(dst_reg(MRF, param_base + 1, ir->shadow_comparitor->type,
 			  WRITEMASK_X),
 		  shadow_comparitor));
@@ -2317,12 +2317,18 @@ vec4_visitor::visit(ir_texture *ir)
 	    emit(MOV(dst_reg(MRF, param_base + 1, type, WRITEMASK_YW), dPdy));
 	    inst->mlen++;
 
-	    if (ir->type->vector_elements == 3) {
+	    if (ir->type->vector_elements == 3 || ir->shadow_comparitor) {
 	       dPdx.swizzle = BRW_SWIZZLE_ZZZZ;
 	       dPdy.swizzle = BRW_SWIZZLE_ZZZZ;
 	       emit(MOV(dst_reg(MRF, param_base + 2, type, WRITEMASK_X), dPdx));
 	       emit(MOV(dst_reg(MRF, param_base + 2, type, WRITEMASK_Y), dPdy));
 	       inst->mlen++;
+
+               if (ir->shadow_comparitor) {
+                  emit(MOV(dst_reg(MRF, param_base + 2,
+                                   ir->shadow_comparitor->type, WRITEMASK_Z),
+                           shadow_comparitor));
+               }
 	    }
 	 } else /* intel->gen == 4 */ {
 	    emit(MOV(dst_reg(MRF, param_base + 1, type, WRITEMASK_XYZ), dPdx));