From: lkcl Date: Fri, 31 Mar 2023 23:04:20 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls012_v1~209 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b5c8ea855d7a2cfd31c3fecf8b0f484b5c8b5199;p=libreriscv.git --- diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn index ff992e4f9..9223fcfa2 100644 --- a/openpower/sv/rfc/ls010.mdwn +++ b/openpower/sv/rfc/ls010.mdwn @@ -256,7 +256,7 @@ This is part of `scalar identity behaviour` described above. The Scalar Power ISA Condition Register is a 64 bit register where the top 32 MSBs (numbered 0:31 in MSB0 numbering) are not used. This convention is -*preserved* (not modified, respected, and thus coipied) +*preserved* in SVP64 and an additional 15 Condition Registers provided in order to store the new CR Fields, CR8-CR15, CR16-CR23 etc. sequentially. The top 32 MSBs in each new SVP64 Condition Register are *also* not used: @@ -289,7 +289,9 @@ Register). Further discussion is out of scope for this version of SVP64. Additionally, a future variant of SVP64 will be applied to the Scalar (Quad-precision and 128-bit) VSX instructions. Element-width overrides are an opportunity to expand the Power ISA to 256-bit, 512-bit and -1024-bit operations. +1024-bit operations, as well as doubling or quadrupling the number +of CSX registers to 128 or 256. Again further discussion is out of +scope for this version of SVP64 --------