From: Richard Earnshaw Date: Mon, 6 Jun 1994 13:14:03 +0000 (+0000) Subject: (arm_reload_out_hi): Rewrite. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b5cc037f4b69e438ccd26b01f1c5e00d8d59599a;p=gcc.git (arm_reload_out_hi): Rewrite. (arm_reload_out_hi): Rewrite. Add support for processors running in big-endian mode. (fp_immediate_constant): Fix typo in argument declaration. From-SVN: r7449 --- diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 996415cff30..9873845421c 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -794,17 +794,26 @@ arm_reload_out_hi (operands) { rtx base = find_replacement (&XEXP (operands[0], 0)); - emit_insn (gen_rtx (SET, VOIDmode, - gen_rtx (MEM, QImode, base), - gen_rtx (SUBREG, QImode, operands[1], 0))); - emit_insn (gen_rtx (SET, VOIDmode, operands[2], - gen_rtx (LSHIFTRT, SImode, - gen_rtx (SUBREG, SImode, operands[1], 0), - GEN_INT (8)))); - emit_insn (gen_rtx (SET, VOIDmode, - gen_rtx (MEM, QImode, - plus_constant (base, 1)), - gen_rtx (SUBREG, QImode, operands[2], 0))); + if (BYTES_BIG_ENDIAN) + { + emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (base, 1)), + gen_rtx (SUBREG, QImode, operands[1], 0))); + emit_insn (gen_lshrsi3 (operands[2], + gen_rtx (SUBREG, SImode, operands[1], 0), + GEN_INT (8))); + emit_insn (gen_movqi (gen_rtx (MEM, QImode, base), + gen_rtx (SUBREG, QImode, operands[2], 0))); + } + else + { + emit_insn (gen_movqi (gen_rtx (MEM, QImode, base), + gen_rtx (SUBREG, QImode, operands[1], 0))); + emit_insn (gen_lshrsi3 (operands[2], + gen_rtx (SUBREG, SImode, operands[1], 0), + GEN_INT (8))); + emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (base, 1)), + gen_rtx (SUBREG, QImode, operands[2], 0))); + } } /* Check to see if a branch is forwards or backwards. Return TRUE if it @@ -845,7 +854,7 @@ arm_insn_not_targeted (insn) when cross compiling. */ char * fp_immediate_constant (x) - rtx (x); + rtx x; { REAL_VALUE_TYPE r; int i;