From: Michael Nolan <mtnolan2640@gmail.com>
Date: Sun, 5 Apr 2020 18:31:48 +0000 (-0400)
Subject: Implement bug 278, comment 1 - better version of EXTS
X-Git-Tag: div_pipeline~1477
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b5e4e847c2841189386da3509949d9206de92f8b;p=soc.git

Implement bug 278, comment 1 - better version of EXTS
---

diff --git a/src/soc/decoder/helpers.py b/src/soc/decoder/helpers.py
index 98b3e672..9cb43b26 100644
--- a/src/soc/decoder/helpers.py
+++ b/src/soc/decoder/helpers.py
@@ -11,7 +11,7 @@ def EXTS(value):
     """ extends sign bit out from current MSB to all 256 bits
     """
     assert isinstance(value, SelectableInt)
-    return SelectableInt(exts(value.value, value.bits) & ((1 << 256)-1), 256)
+    return exts(value.value, value.bits)
 
 def EXTS64(value):
     """ extends sign bit out from current MSB to 64 bits
diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 874a0697..5b1c4c99 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -110,7 +110,9 @@ class ISACaller:
         for name, output in zip(output_names, results):
             regnum = yield getattr(self.decoder, name)
             print('writing reg %d' % regnum)
-            self.gpr[regnum] = output.narrow(64)
+            if isinstance(output, int):
+                output = SelectableInt(output, 64)
+            self.gpr[regnum] = output
 
 
 def inject():
diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index aa6f23ae..12db9847 100644
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -9,7 +9,7 @@ from soc.simulator.program import Program
 from soc.decoder.isa.caller import ISACaller, inject
 from soc.decoder.selectable_int import SelectableInt
 from soc.decoder.orderedset import OrderedSet
-from soc.decoder.isa import ISA
+from soc.decoder.isa.all import ISA
 
 
 class Register: