From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 28 Jun 2019 18:16:15 +0000 (-0700)
Subject: Add missing CHANGELOG entries
X-Git-Tag: working-ls180~1235
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b5f1bd0df1a467679a93d05604c6cc72696854ba;p=yosys.git

Add missing CHANGELOG entries
---

diff --git a/CHANGELOG b/CHANGELOG
index c280f4f12..15dd5d002 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -23,6 +23,9 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "muxcover -nopartial"
     - Added "muxpack" pass
     - Added "pmux2shiftx -norange"
+    - Added "synth_xilinx -nocarry"
+    - Added "synth_xilinx -nowidelut"
+    - Added "synth_ecp5 -nowidelut"
     - Added "write_xaiger" backend
     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
     - Added "synth_xilinx -abc9" (experimental)