From: Mikolaj Wielgus Date: Mon, 20 Dec 2021 18:07:32 +0000 (+0000) Subject: Generate variable declaration in some missing places X-Git-Tag: sv_maxu_works-initial~615 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b5f4f7c6e66cccfdddd14cd2997a2a292893b597;p=openpower-isa.git Generate variable declaration in some missing places --- diff --git a/src/openpower/decoder/test/_pyrtl.py b/src/openpower/decoder/test/_pyrtl.py index a384c3ac..07d68a96 100644 --- a/src/openpower/decoder/test/_pyrtl.py +++ b/src/openpower/decoder/test/_pyrtl.py @@ -405,7 +405,7 @@ class _StatementCompiler(StatementVisitor, _Compiler): output_indexes = [state.get_signal(signal) for signal in stmt._lhs_signals()] emitter = _PythonEmitter() for signal_index in output_indexes: - emitter.append(f"next_{signal_index} = slots[{signal_index}].next") + emitter.append(f"uint64_t next_{signal_index} = slots[{signal_index}].next") compiler = cls(state, emitter) compiler(stmt) for signal_index in output_indexes: @@ -471,7 +471,7 @@ class _FragmentCompiler: for signal in domain_signals: signal_index = self.state.get_signal(signal) - emitter.append(f"next_{signal_index} = slots[{signal_index}].next;") + emitter.append(f"uint64_t next_{signal_index} = slots[{signal_index}].next;") _StatementCompiler(self.state, emitter)(domain_stmts)