From: Kevin Lim <ktlim@umich.edu>
Date: Wed, 6 Dec 2006 19:23:31 +0000 (-0500)
Subject: Fix for MIPS_SE/m5.fast compile.
X-Git-Tag: m5_2.0_beta2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b618e733bd580391702a844404417f9723b94588;p=gem5.git

Fix for MIPS_SE/m5.fast compile.

--HG--
extra : convert_revision : dbb893250974ac6db7b6c1ba67263fd35098ca43
---

diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 43305f962..f400d757b 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -1197,16 +1197,16 @@ DefaultCommit<Impl>::getInsts()
              rename_idx < fromRename->size;
              rename_idx++) {
             DynInstPtr inst = fromRename->insts[rename_idx];
-            int tid = inst->threadNumber;
 
             if (!inst->isSquashed()) {
                 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
-                        "skidBuffer.\n", inst->readPC(), inst->seqNum, tid);
+                        "skidBuffer.\n", inst->readPC(), inst->seqNum,
+                        inst->threadNumber);
                 skidBuffer.push(inst);
             } else {
                 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
                         "squashed, skipping.\n",
-                        inst->readPC(), inst->seqNum, tid);
+                        inst->readPC(), inst->seqNum, inst->threadNumber);
             }
         }
     }