From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 9 Dec 2021 09:53:25 +0000 (+0000)
Subject: include SPR.TB in SPR FU
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b62561e141cc169e8e67f3e360b907e119d0b328;p=soc.git

include SPR.TB in SPR FU
---

diff --git a/src/soc/fu/spr/main_stage.py b/src/soc/fu/spr/main_stage.py
index a73c6be9..64676e44 100644
--- a/src/soc/fu/spr/main_stage.py
+++ b/src/soc/fu/spr/main_stage.py
@@ -57,7 +57,7 @@ class SPRMainStage(PipeModBase):
                 with m.Switch(spr):
                     # fast SPRs first
                     with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0,
-                                SPR.SRR1, SPR.XER, SPR.DEC):
+                                SPR.SRR1, SPR.XER, SPR.DEC, SPR.TB):
                         comb += fast1_o.data.eq(a_i)
                         comb += fast1_o.ok.eq(1)
                         # XER is constructed