From: Florent Kermarrec Date: Wed, 9 Oct 2019 10:05:10 +0000 (+0200) Subject: cpu: add default io_regions to CPUNone (all address range can be used as IO) X-Git-Tag: 24jan2021_ls180~933 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b627a8fe71b55f1987a9cd5181da14cddd3203c1;p=litex.git cpu: add default io_regions to CPUNone (all address range can be used as IO) --- diff --git a/litex/soc/cores/cpu/__init__.py b/litex/soc/cores/cpu/__init__.py index 236dba4b..6aeb6ba5 100644 --- a/litex/soc/cores/cpu/__init__.py +++ b/litex/soc/cores/cpu/__init__.py @@ -17,10 +17,12 @@ class CPU(Module): linker_output_format = None interrupts = {} mem_map = {} + io_regions = {} class CPUNone(CPU): data_width = 32 reset_address = 0x00000000 + io_regions = {0x00000000: 0xf0000000} # origin, length # CPUS --------------------------------------------------------------------------------------------- diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index a340e2db..55278bbc 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -198,6 +198,7 @@ class SoCCore(Module): self.comb += self.cpu.reset.eq(self.ctrl.reset) else: self.add_cpu(cpu.CPUNone()) + self.soc_io_regions.update(self.cpu.io_regions) # Add user's interrupts (needs to be done after CPU interrupts are allocated) for _name, _id in self.interrupt_map.items():