From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 16 May 2019 12:21:18 +0000 (+0200)
Subject: Merge pull request #1013 from antmicro/parameter_attributes
X-Git-Tag: yosys-0.9~119
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b6345b111d994ff0de1bcd91379db1c289feb03b;p=yosys.git

Merge pull request #1013 from antmicro/parameter_attributes

Support for attributes on parameters and localparams for Verilog frontend
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b6345b111d994ff0de1bcd91379db1c289feb03b