From: Marek Olšák <marek.olsak@amd.com>
Date: Tue, 7 Jan 2020 02:39:14 +0000 (-0500)
Subject: radeonsi: determine accurately if line stippling is enabled for performance
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b64a3240c2f73f599524d1ee5794a393a380acdc;p=mesa.git

radeonsi: determine accurately if line stippling is enabled for performance

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
---

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 24714576f00..8d2dca1d197 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -923,6 +923,10 @@ static void *si_create_rs_state(struct pipe_context *ctx,
 				    !(state->cull_face & PIPE_FACE_FRONT)) ||
 				   (state->fill_back != PIPE_POLYGON_MODE_FILL &&
 				    !(state->cull_face & PIPE_FACE_BACK));
+	rs->polygon_mode_is_lines = (state->fill_front == PIPE_POLYGON_MODE_LINE &&
+				     !(state->cull_face & PIPE_FACE_FRONT)) ||
+				    (state->fill_back == PIPE_POLYGON_MODE_LINE &&
+				     !(state->cull_face & PIPE_FACE_BACK));
 	rs->pa_sc_line_stipple = state->line_stipple_enable ?
 				S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
 				S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
@@ -1075,9 +1079,6 @@ static void si_bind_rs_state(struct pipe_context *ctx, void *state)
 	    old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
 		si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
 
-	sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
-		rs->line_stipple_enable;
-
 	if (old_rs->clip_plane_enable != rs->clip_plane_enable ||
 	    old_rs->rasterizer_discard != rs->rasterizer_discard ||
 	    old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index d334a5196d1..05f2576b970 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -95,6 +95,7 @@ struct si_state_rasterizer {
 	unsigned		depth_clamp_any:1;
 	unsigned		provoking_vertex_first:1;
 	unsigned		polygon_mode_enabled:1;
+	unsigned		polygon_mode_is_lines:1;
 };
 
 struct si_dsa_stencil_ref_part {
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 101d8d27420..9702efa68de 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -501,6 +501,16 @@ static void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
 	}
 }
 
+static bool si_is_line_stipple_enabled(struct si_context *sctx)
+{
+	struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
+
+	return rs->line_stipple_enable &&
+	       sctx->current_rast_prim != PIPE_PRIM_POINTS &&
+	       (rs->polygon_mode_is_lines ||
+		util_prim_is_lines(sctx->current_rast_prim));
+}
+
 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
 					  const struct pipe_draw_info *info,
 					  enum pipe_prim_type prim,
@@ -529,6 +539,7 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
 		  si_num_prims_for_vertices(info, prim) < primgroup_size));
 	key.u.primitive_restart = primitive_restart;
 	key.u.count_from_stream_output = info->count_from_stream_output != NULL;
+	key.u.line_stipple_enabled = si_is_line_stipple_enabled(sctx);
 
 	ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
 			     S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
@@ -747,7 +758,7 @@ static void gfx10_emit_ge_cntl(struct si_context *sctx, unsigned num_patches)
 			  S_03096C_BREAK_WAVE_AT_EOI(key.u.uses_tess && key.u.tess_uses_prim_id);
 	}
 
-	ge_cntl |= S_03096C_PACKET_TO_ONE_PA(key.u.line_stipple_enabled);
+	ge_cntl |= S_03096C_PACKET_TO_ONE_PA(si_is_line_stipple_enabled(sctx));
 
 	if (ge_cntl != sctx->last_multi_vgt_param) {
 		radeon_set_uconfig_reg(sctx->gfx_cs, R_03096C_GE_CNTL, ge_cntl);