From: Clifford Wolf Date: Fri, 15 Aug 2014 12:18:40 +0000 (+0200) Subject: Renamed $lut ports to follow A-Y naming scheme X-Git-Tag: yosys-0.4~253 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b64b38eea2e9a7de30d6045f069c86bf4446134f;p=yosys.git Renamed $lut ports to follow A-Y naming scheme --- diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index 386d68d8b..b9b68b979 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -188,13 +188,13 @@ struct BlifDumper if (!config->icells_mode && cell->type == "$lut") { fprintf(f, ".names"); - auto &inputs = cell->getPort("\\I"); + auto &inputs = cell->getPort("\\A"); auto width = cell->parameters.at("\\WIDTH").as_int(); log_assert(inputs.size() == width); for (int i = 0; i < inputs.size(); i++) { fprintf(f, " %s", cstr(inputs.extract(i, 1))); } - auto &output = cell->getPort("\\O"); + auto &output = cell->getPort("\\Y"); log_assert(output.size() == 1); fprintf(f, " %s", cstr(output)); fprintf(f, "\n"); diff --git a/kernel/celltypes.h b/kernel/celltypes.h index e30ceb8b1..402d6ea76 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -88,7 +88,7 @@ struct CellTypes std::vector unary_ops = { "$not", "$pos", "$bu0", "$neg", "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool", - "$logic_not", "$slice" + "$logic_not", "$slice", "$lut" }; std::vector binary_ops = { @@ -108,7 +108,6 @@ struct CellTypes for (auto type : std::vector({"$mux", "$pmux"})) setup_type(type, {"\\A", "\\B", "\\S"}, {"\\Y"}, false); - setup_type("$lut", {"\\I"}, {"\\O"}, false); setup_type("$assert", {"\\A", "\\EN"}, {}, false); } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 614ea770b..d118b6257 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -615,8 +615,8 @@ namespace { if (cell->type == "$lut") { param("\\LUT"); - port("\\I", param("\\WIDTH")); - port("\\O", 1); + port("\\A", param("\\WIDTH")); + port("\\Y", 1); check_expected(); return; } @@ -1388,8 +1388,8 @@ RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, R RTLIL::Cell *cell = addCell(name, "$lut"); cell->parameters["\\LUT"] = lut; cell->parameters["\\WIDTH"] = sig_i.size(); - cell->setPort("\\I", sig_i); - cell->setPort("\\O", sig_o); + cell->setPort("\\A", sig_i); + cell->setPort("\\Y", sig_o); return cell; } diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc index bc8f343a5..1fbb5720d 100644 --- a/passes/abc/blifparse.cc +++ b/passes/abc/blifparse.cc @@ -195,8 +195,8 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut"); cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size()); cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size()); - cell->setPort("\\I", input_sig); - cell->setPort("\\O", output_sig); + cell->setPort("\\A", input_sig); + cell->setPort("\\Y", output_sig); lutptr = &cell->parameters.at("\\LUT"); lut_default_state = RTLIL::State::Sx; continue; diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 4b3317a76..8c0a54e4e 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -955,13 +955,13 @@ endmodule // -------------------------------------------------------- `ifndef SIMLIB_NOLUT -module \$lut (I, O); +module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; -input [WIDTH-1:0] I; -output reg O; +input [WIDTH-1:0] A; +output reg Y; wire lut0_out, lut1_out; @@ -969,18 +969,18 @@ generate if (WIDTH <= 1) begin:simple assign {lut1_out, lut0_out} = LUT; end else begin:complex - \$lut #( .WIDTH(WIDTH-1), .LUT(LUT ) ) lut0 ( .I(I[WIDTH-2:0]), .O(lut0_out) ); - \$lut #( .WIDTH(WIDTH-1), .LUT(LUT >> (2**(WIDTH-1))) ) lut1 ( .I(I[WIDTH-2:0]), .O(lut1_out) ); + \$lut #( .WIDTH(WIDTH-1), .LUT(LUT ) ) lut0 ( .A(A[WIDTH-2:0]), .Y(lut0_out) ); + \$lut #( .WIDTH(WIDTH-1), .LUT(LUT >> (2**(WIDTH-1))) ) lut1 ( .A(A[WIDTH-2:0]), .Y(lut1_out) ); end if (WIDTH > 0) begin:lutlogic always @* begin - casez ({I[WIDTH-1], lut0_out, lut1_out}) - 3'b?11: O = 1'b1; - 3'b?00: O = 1'b0; - 3'b0??: O = lut0_out; - 3'b1??: O = lut1_out; - default: O = 1'bx; + casez ({A[WIDTH-1], lut0_out, lut1_out}) + 3'b?11: Y = 1'b1; + 3'b?00: Y = 1'b0; + 3'b0??: Y = lut0_out; + 3'b1??: Y = lut1_out; + default: Y = 1'bx; endcase end end diff --git a/techlibs/xilinx/cells.v b/techlibs/xilinx/cells.v index 5bf8ccd86..d19be0db7 100644 --- a/techlibs/xilinx/cells.v +++ b/techlibs/xilinx/cells.v @@ -10,41 +10,41 @@ module \$_DFF_P_ (D, C, Q); endmodule -module \$lut (I, O); +module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; - input [WIDTH-1:0] I; - output O; + input [WIDTH-1:0] A; + output Y; generate if (WIDTH == 1) begin:lut1 - LUT1 #(.INIT(LUT)) fpga_lut (.O(O), - .I0(I[0])); + LUT1 #(.INIT(LUT)) fpga_lut (.O(Y), + .I0(A[0])); end else if (WIDTH == 2) begin:lut2 - LUT2 #(.INIT(LUT)) fpga_lut (.O(O), - .I0(I[0]), .I1(I[1])); + LUT2 #(.INIT(LUT)) fpga_lut (.O(Y), + .I0(A[0]), .I1(A[1])); end else if (WIDTH == 3) begin:lut3 - LUT3 #(.INIT(LUT)) fpga_lut (.O(O), - .I0(I[0]), .I1(I[1]), .I2(I[2])); + LUT3 #(.INIT(LUT)) fpga_lut (.O(Y), + .I0(A[0]), .I1(A[1]), .I2(A[2])); end else if (WIDTH == 4) begin:lut4 - LUT4 #(.INIT(LUT)) fpga_lut (.O(O), - .I0(I[0]), .I1(I[1]), .I2(I[2]), - .I3(I[3])); + LUT4 #(.INIT(LUT)) fpga_lut (.O(Y), + .I0(A[0]), .I1(A[1]), .I2(A[2]), + .I3(A[3])); end else if (WIDTH == 5) begin:lut5 - LUT5 #(.INIT(LUT)) fpga_lut (.O(O), - .I0(I[0]), .I1(I[1]), .I2(I[2]), - .I3(I[3]), .I4(I[4])); + LUT5 #(.INIT(LUT)) fpga_lut (.O(Y), + .I0(A[0]), .I1(A[1]), .I2(A[2]), + .I3(A[3]), .I4(A[4])); end else if (WIDTH == 6) begin:lut6 - LUT6 #(.INIT(LUT)) fpga_lut (.O(O), - .I0(I[0]), .I1(I[1]), .I2(I[2]), - .I3(I[3]), .I4(I[4]), .I5(I[5])); + LUT6 #(.INIT(LUT)) fpga_lut (.O(Y), + .I0(A[0]), .I1(A[1]), .I2(A[2]), + .I3(A[3]), .I4(A[4]), .I5(A[5])); end else begin:error wire _TECHMAP_FAIL_ = 1; end