From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 21 Apr 2020 22:44:56 +0000 (-0700)
Subject: abc9_ops: move assert
X-Git-Tag: working-ls180~549^2~17
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b65610fb628cfd38edcab3c64507477a58cbdd10;p=yosys.git

abc9_ops: move assert
---

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 37d0528c1..b3f5b9919 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -263,9 +263,9 @@ void prep_bypass(RTLIL::Design *design)
 			auto derived_type = inst_module->derive(design, cell->parameters);
 			inst_module = design->module(derived_type);
 			log_assert(inst_module);
-			log_assert(!inst_module->get_blackbox_attribute(true /* ignore_wb */));
 			if (!inst_module->get_bool_attribute(ID::abc9_bypass))
 				continue;
+			log_assert(!inst_module->get_blackbox_attribute(true /* ignore_wb */));
 
 
 			// The idea is to create two techmap designs, one which maps: