From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 20 May 2019 08:07:44 +0000 (+0100)
Subject: attempting to work out FU-FU matrix connections
X-Git-Tag: div_pipeline~2008
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b65d6b3d21ad4032bf00e97fa750098cf20d93a4;p=soc.git

attempting to work out FU-FU matrix connections
---

diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index f1c87098..31f267a9 100644
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -415,7 +415,6 @@ def scoreboard_sim(dut, alusim):
         yield
         yield
         yield
-        yield
 
     yield
     yield from print_reg(dut, [1,2,3])
diff --git a/src/scoreboard/fu_fu_matrix.py b/src/scoreboard/fu_fu_matrix.py
index 965503a9..239f26b7 100644
--- a/src/scoreboard/fu_fu_matrix.py
+++ b/src/scoreboard/fu_fu_matrix.py
@@ -67,11 +67,11 @@ class FUFUDepMatrix(Elaboratable):
         # ---
         # connect FU Pending
         # ---
-        for x in range(self.n_fu_col):
+        for y in range(self.n_fu_row):
             fu = fur[x]
             rd_wait_o = []
             wr_wait_o = []
-            for y in range(self.n_fu_row):
+            for x in range(self.n_fu_col):
                 dc = dm[x][y]
                 # accumulate cell outputs rd/wr-pending
                 rd_wait_o.append(dc.rd_wait_o)
@@ -81,7 +81,7 @@ class FUFUDepMatrix(Elaboratable):
                          fu.wr_pend_i.eq(Cat(*wr_wait_o)),
                         ]
         # ---
-        # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i
+        # connect Dependency Matrix issue to module issue
         # ---
         for y in range(self.n_fu_row):
             issue_i = []
@@ -98,19 +98,29 @@ class FUFUDepMatrix(Elaboratable):
         for x in range(self.n_fu_col):
             go_rd_i = []
             go_wr_i = []
-            rd_pend_i = []
-            wr_pend_i = []
             for y in range(self.n_fu_row):
                 dc = dm[x][y]
-                # accumulate cell rd_pend/wr_pend/go_rd/go_wr
-                rd_pend_i.append(dc.rd_pend_i)
-                wr_pend_i.append(dc.wr_pend_i)
+                # accumulate cell go_rd/go_wr
                 go_rd_i.append(dc.go_rd_i)
                 go_wr_i.append(dc.go_wr_i)
             # wire up inputs from module to row cell inputs (Cat is gooood)
             m.d.comb += [Cat(*go_rd_i).eq(self.go_rd_i),
                          Cat(*go_wr_i).eq(self.go_wr_i),
-                         Cat(*rd_pend_i).eq(self.rd_pend_i),
+                        ]
+
+        # ---
+        # connect Matrix pending
+        # ---
+        for y in range(self.n_fu_row):
+            rd_pend_i = []
+            wr_pend_i = []
+            for x in range(self.n_fu_col):
+                dc = dm[x][y]
+                # accumulate cell rd_pend/wr_pend/go_rd/go_wr
+                rd_pend_i.append(dc.rd_pend_i)
+                wr_pend_i.append(dc.wr_pend_i)
+            # wire up inputs from module to row cell inputs (Cat is gooood)
+            m.d.comb += [Cat(*rd_pend_i).eq(self.rd_pend_i),
                          Cat(*wr_pend_i).eq(self.wr_pend_i),
                         ]