From: SergeyDegtyar <sndegtyar@gmail.com>
Date: Wed, 25 Sep 2019 11:43:26 +0000 (+0300)
Subject: Change sync controls to async.
X-Git-Tag: working-ls180~1047^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b66364ada279c1fb81583003001b332dd4521f93;p=yosys.git

Change sync controls to async.
---

diff --git a/tests/ice40/adffs.v b/tests/ice40/adffs.v
index 05e68caf7..09dc36001 100644
--- a/tests/ice40/adffs.v
+++ b/tests/ice40/adffs.v
@@ -27,7 +27,7 @@ module dffs
     initial begin
       q = 0;
     end
-	always @( posedge clk )
+	always @( posedge clk, posedge pre )
 		if ( pre )
 			q <= 1'b1;
 		else
@@ -39,9 +39,9 @@ module ndffnr
     initial begin
       q = 0;
     end
-	always @( negedge clk )
-		if ( !clr )
-			q <= 1'b0;
+	always @( negedge clk, negedge pre )
+		if ( !pre )
+			q <= 1'b1;
 		else
             q <= d;
 endmodule
diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys
index f82da6b14..548060b66 100644
--- a/tests/ice40/adffs.ys
+++ b/tests/ice40/adffs.ys
@@ -4,8 +4,8 @@ flatten
 equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
-select -assert-count 1 t:SB_DFFNSR
+select -assert-count 1 t:SB_DFFNS
 select -assert-count 2 t:SB_DFFR
-select -assert-count 1 t:SB_DFFSS
-select -assert-count 1 t:SB_LUT4
-select -assert-none t:SB_DFFNSR t:SB_DFFR t:SB_DFFSS t:SB_LUT4 %% t:* %D
+select -assert-count 1 t:SB_DFFS
+select -assert-count 2 t:SB_LUT4
+select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D